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| 型號(hào)： | RH8053GC029512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 40/81頁 |
| 文件大?。?/td> | 598K |
| 代理商： | RH8053GC029512 |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
40
4.
System Signal Simulations
Many scenarios have been simulated to generate a set of GTL+ processor system bus layout
guidelines, which are available in the
Mobile Pentium
III
Processor GTL+ System Bus Layout
Guideline.
Systems must be simulated using the IBIS model to determine if they are compliant
with this specification.
4.1
System Bus Clock (BCLK) and PICCLK AC Signal
Quality Specifications
Table 22 and Figure 15 show the signal quality for the system bus clock (BCLK) signal, and
Table 23 and Figure 15 show the signal quality for the APIC bus clock (PICCLK) signal at the
processor. BCLK and PICCLK are 2.5V clocks.
Table 22. BCLK Signal Quality Specifications
Symbol
Parameter
Min
Max Unit
Figure
Notes
V1
V
IL,BCLK
0.5
V
Figure 15
Note 1
V2
V
IH,BCLK
2.0
V
Figure 15
Note 1
V3
V
IN
Absolute Voltage Range
-0.7
3.5
V
Figure 15
Undershoot/Overshoot,
Note 2
V4
BCLK Rising Edge Ringback
2.0
V
Figure 15
Absolute Value, Note 3
V5
NOTES:
1.
2.
BCLK Falling Edge Ringback
0.5
V
Figure 15
Absolute Value, Note 3
The clock must rise/fall monotonically between V
IL,BCLK
and V
IH,BCLK
.
These specifications apply only when BCLK is running, see Table 12 for the DC specifications for when
BCLK is stopped. BCLK may not be above V
IH,BCLK,max
or below V
IL,BCLK,min
for more than 50% of the
clock cycle.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can go to after passing the V
IH,BCLK
(rising) or V
IL,BCLK
(falling) voltage limits.
3.
Table 23. PICCLK Signal Quality Specifications
Symbol
Parameter
Min Max Unit Figure
Notes
V1
V
IL25
0.7
V
Figure 15 Note 1
V2
V
IH25
2.0
V
Figure 15 Note 1
V3
V
IN
Absolute Voltage Range
-0.7 3.5
V
Figure 15 Undershoot,Overshoot, Note 2
V4
PICCLK Rising Edge Ringback
2.0
V
Figure 15 Absolute Value, Note 3
V5
NOTES:
1.
2.
PICCLK Falling Edge Ringback
0.7
V
Figure 15 Absolute Value, Note 3
The clock must rise/fall monotonically between V
IL25
and V
IH25
.
These specifications apply only when PICCLK is running, see Table 12 for the DC specifications for when
PICCLK is stopped. PICCLK may not be above V
IH25,max
or below V
IL25,min
for more than 50% of the clock
cycle.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the PICCLK signal can go to after passing the V
IH25
(rising) or V
IL25
(falling) voltage limits.
3.
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