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| 型號(hào)： | RH8053GC029512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 33/81頁(yè) |
| 文件大小： | 598K |
| 代理商： | RH8053GC029512 |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
33
Table 20. Quick Start/Deep Sleep AC Specifications
1
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol
Parameter
Min Max Unit
Figure
Notes
T45
Stop Grant Cycle Completion to Clock Stop
100
BCLKs
Figure 13
T46
Stop Grant Cycle Completion to Input Signals Stable
0
μ
s
Figure 13
T47
Deep Sleep PLL Lock Latency
0
30
μ
s
Figure 13,
Figure 14
Note 2
T48
STPCLK# Hold Time from PLL Lock
0
ns
Figure 13
T49
NOTES:
1.
2.
Input Signal Hold Time from STPCLK# Deassertion
8
BCLKs
Figure 13
Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
The BCLK Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Table 21. Stop Grant/Sleep/Deep Sleep AC Specifications
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol
Parameter
Min Max Unit
Figure
T50
SLP# Signal Hold Time from Stop Grant Cycle Completion 100
BCLKs
Figure 14
T51
SLP# Assertion to Input Signals Stable
0
ns
Figure 14
T52
SLP# Assertion to Clock Stop
10
BCLKs
Figure 14
T54
SLP# Hold Time from PLL Lock
0
ns
Figure 14
T55
STPCLK# Hold Time from SLP# Deassertion
10
BCLKs
Figure 14
T56
Input Signal Hold Time from SLP# Deassertion
10
BCLKs
Figure 14
NOTE:
Input signals other than RESET# must be held constant in the Sleep state. The BCLK Settling Time
specification (T60) applies to Deep Sleep state exit under all conditions.
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