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| 型號(hào)： | RH8053GC029512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 31/81頁(yè) |
| 文件大?。?/td> | 598K |
| 代理商： | RH8053GC029512 |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
31
Table 18. APIC Bus Signal AC Specifications
1
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T21
PICCLK Frequency
2
33.3
MHz
Note 2
T22
PICCLK Period
30
500
ns
Figure 5
T23
PICCLK High Time
10.5
ns
Figure 5
at>1.7V
T24
PICCLK Low Time
10.5
ns
Figure 5
at<0.7V
T25
PICCLK Rise Time
0.25
3.0
ns
Figure 5
(0.7V – 1.7V)
T26
PICCLK Fall Time
0.25
3.0
ns
Figure 5
(1.7V – 0.7V)
T27
PICD[1:0] Setup Time
8.0
ns
Figure 8
Note 3
T28
PICD[1:0] Hold Time
2.5
ns
Figure 8
Note 3
T29
NOTES:
1.
PICD[1:0] Valid Delay
1.5
10.0
ns
Figure 7
Notes 3, 4, 5
All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.25V. All CMOS signals are
referenced at 0.75V.
The minimum frequency is 2 MHz when PICD0 is at 1.5V at reset. If PICD0 is strapped to V
SS
at reset then
the minimum frequency is 0 MHz.
Referenced to PICCLK Rising Edge.
For Open-drain signals, Valid Delay is synonymous with Float Delay.
Valid delay timings for these signals are specified into 150
to 1.5V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.
2.
3.
4.
5.
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