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參數(shù)資料
| 型號： | PPC440GRX-STA400TZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680 |
| 封裝： | 35 MM, THERMALLY ENHANCED, PLASTIC, BGA-680 |
| 文件頁數(shù)： | 84/88頁 |
| 文件大?。?/td> | 1367K |
| 代理商： | PPC440GRX-STA400TZ |
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440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
85
Preliminary Data Sheet
DDR SDRAM Read Operation
The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the
data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to
ensure that the rising and falling edges of these strobes are in the middle of the valid window of data.
DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the
PPC440GRx. The edges of these strobe signals are aligned with the data output by the SDRAM devices.
In order to reliably latch the data into a synchronizing FIFO, the PPC440GRx produces an internal, delayed version
of DQS. The amount of delay is user programmable. In the example shown in Figure 12, DDR SDRAM DQS Read
Timing, the delay is set to approximately 25% of the system clock. A delay compensation circuit in the PPC440GRx
keeps this delay constant.
Figure 12. DDR SDRAM DQS Read Timing
Table 27. I/O Timing—DDR SDRAM TSD and THD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 166MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (6ns x 0.25 = 1.5 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD 1.5 + 0.25TCYC).
Signal Names
Reference Signal
TSD (ns)
THD (ns)
MemData00:07, DM0
DQS0
1.37
1.23
MemData08:15, DM1
DQS1
1.41
1.18
MemData16:23, DM2
DQS2
1.40
1.17
MemData24:31, DM3
DQS3
1.41
1.20
MemData32:39, DM4
DQS4
1.45
1.18
MemData40:47, DM5
DQS5
1.40
1.18
MemData48:55, DM6
DQS6
1.46
1.17
MemData56:63, DM7
DQS7
1.45
1.10
ECC0:7, DM8
DQS8
1.46
1.18
DQS delay
MemClkOut
DQS
MemData
Delayed DQS
(data strobe)
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相關代理商/技術參數(shù) |
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| PPC440GRX-STA533E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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| PPC440GRX-SUA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-SUA400EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
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