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參數(shù)資料
| 型號(hào)： | PPC440GRX-STA400TZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680 |
| 封裝： | 35 MM, THERMALLY ENHANCED, PLASTIC, BGA-680 |
| 文件頁數(shù)： | 80/88頁 |
| 文件大?。?/td> | 1367K |
| 代理商： | PPC440GRX-STA400TZ |
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440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
81
Preliminary Data Sheet
When using unbufferred DIMMS, the loading on the address bus will be considerably greater than the clock (up to
18 loads for double-sided DIMMs). In this case, it is strongly suggested that a delay of 500ps in the clock path so
that the Address/Command setup time at the DIMMs can be met. This delay is sufficient to meet the setup time,
without having to change the programmable delay (internal to the PPC440GRx) between the DQS/DQ/DM and the
clock (assuming nominal settings as specified in the PPC440GRx Users Manual). While the clock is now 500ps
later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for TDQSS
(± 0.25 cycle, or 1.5ns at 166MHz). In the case where it is not possible to anticipate which kind of DIMMs may be
employed in a system, it is always safe to use this 500ps clock delay, since registered DIMMs (the least heavily
loaded) will have more than enough margin (almost 1/2 cycle) to accommodate the slight decrease in address hold
time.
Termination Model
Figure 10. DDR SDRAM Simulation Signal Termination Model
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
Table 23. DDR SDRAM Output Driver Specifications (Sheet 1 of 2)
Signal Path
Output Current (mA)
I/O H (maximum)
I/O L (maximum)
Write Data
MemData00:63
10
ECC0:7
10
DM0:8
10
MemClkOut
10
MemAddr00:13
10
BA0:2
10
10pF
MemClkOut
120
Ω
50
Ω
30pF
Addr/Ctrl/Data/DQS/DM (DDR1)
VTT = SOVDD/2
PPC440GRx
Addr/Ctrl (DDR2)
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
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