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參數(shù)資料
| 型號： | PPC440GRX-STA400TZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680 |
| 封裝： | 35 MM, THERMALLY ENHANCED, PLASTIC, BGA-680 |
| 文件頁數(shù)： | 58/88頁 |
| 文件大?。?/td> | 1367K |
| 代理商： | PPC440GRX-STA400TZ |
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440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
61
Preliminary Data Sheet
NAND Flash Interface
NFALE
Address Latch Enable.
O
3.3V LVTTL
1
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
O
3.3V LVTTL
1
NFCLE
Command Latch Enable.
Latches operational commands into the NAND Flash.
O3.3V LVTTL
1
NFRdyBusy
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-OR connected from all NAND Flash
devices.
I3.3V LVTTL
1
NFREn
Read Enable.
Data is latched on the rising edge.
O3.3V LVTTL
1
NFWEn
Write Enable.
Data is latched on the rising edge.
O3.3V LVTTL
1
Serial Peripheral Interface
SCPClkOut
Clock output.
I/O
3.3V LVTTL
SCPDI
Data input.
I/O
3.3V LVTTL
SCPDO
Data output.
O
3.3V LVTTL
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
I/O
3.3V LVTTL
1
IRQ5
External interrupt request 5.
I
3.3V LVTTL
Rcvr
1, 5
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
1
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
w/pull-up
1
TDI
Test Data In.
I
3.3V LVTTL
w/pull-up
1, 4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL
w/pull-up
1
TRST
Test Reset.
I
3.3V LVTTL
w/pull-up
1, 5
Table 9. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to OV
DD (EOVDD for Ethernet)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to OV
DD (EOVDD for Ethernet)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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