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參數(shù)資料
| 型號： | PPC440GRX-STA400TZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680 |
| 封裝： | 35 MM, THERMALLY ENHANCED, PLASTIC, BGA-680 |
| 文件頁數(shù)： | 82/88頁 |
| 文件大?。?/td> | 1367K |
| 代理商： | PPC440GRX-STA400TZ |
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440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
83
Preliminary Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 11. DDR SDRAM Write Cycle Timing
Note: The timing data in the following tables is based on simulation runs using Einstimer.
DQS
MemData
PLB Clk
MemClkOut
Addr/Cmd
TSK
TSA
THA
TDS
TSD
THD
TSD
THD
TSA = Setup time for address and command signals to MemClkOut
TSK = Delay from falling edge of MemClkOut to rising/falling edge of signal (skew)
THA = Hold time for address and command signals from MemClkOut
TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
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