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參數(shù)資料
| 型號： | PPC440GRX-STA400TZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680 |
| 封裝： | 35 MM, THERMALLY ENHANCED, PLASTIC, BGA-680 |
| 文件頁數(shù)： | 71/88頁 |
| 文件大?。?/td> | 1367K |
| 代理商： | PPC440GRX-STA400TZ |
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440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
73
Preliminary Data Sheet
I/O Specifications
Table 20. Peripheral Interface Clock Timings
Parameter
Min
Max
Units
Notes
PCIClk frequency (asynchronous mode)
–
66.66
MHz
PCIClk period (asynchronous mode)
15
–
ns
PCIClk high time
40% of nominal period
60% of nominal period
ns
PCIClk low time
40% of nominal period
60% of nominal period
ns
GMCMDClk frequency
–
2.5
MHz
GMCMDClk period
400
–
ns
GMCMDClk high time
160
–
ns
GMCMDClk low time
160
–
ns
GMCTxClk frequency MII
2.5
25
MHz
GMCTxClk period MII
40
400
ns
GMCTxClk high time
35% of nominal period
–
ns
GMCTxClk low time
35% of nominal period
–
ns
GMCRxClk frequency MII
2.5
25
MHz
GMCRxClk period MII
40
400
ns
GMCRxClk high time
35% of nominal period
–
ns
GMCRxClk low time
35% of nominal period
–
ns
GMCRefClk frequency
–
125
MHz
GMCRefClk period
8
–
MHz
GMCRefClk high time
40% of nominal period
60% of nominal period
ns
2
GMCRefClk low time
40% of nominal period
60% of nominal period
ns
2
PerClk (and OPB Clock) frequency (for ext. master or sync.
slaves)
33.33MHz
83.33
MHz
GMCRefClk Edge stability (cycle-to-cycle jitter)
–
+0.15
ns
GMCRefClk Slew Rate
2
–
V/ns
PerClk period
12
30
ns
PerClk high time
50% of nominal period
66% of nominal period
ns
PerClk low time
33% of nominal period
50% of nominal period
ns
UARTSerClk frequency
–
1000 / (2TOPB
1+2ns)
MHz
1
UARTSerClk period
2TOPB
1+2
–ns
1
UARTSerClk high time
TOPB
1+1
–ns
1
UARTSerClk low time
TOPB
1+1
–ns
1
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