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參數(shù)資料
| 型號： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 8/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標準包裝： | 168 |
| 系列： | UltraLo™ |
| 應用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應商設備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 16 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
5 FUNCTIONAL DESCRIPTION
Multiple virtual PCI-to-PCI Bridges (VPPB), connected by a virtual PCI bus, reside in the Switch. Each VPPB
contains the complete PCIe architecture layers that consist of the physical, data link, and transaction layer. The
packets entering the Switch via one of VPPBs are first converted from serial bit-stream into parallel bus signals in
physical layer, stripped off the link-related header by data link layer, and then relayed up to the transaction layer to
extract out the transaction header. According to the address or ID embedded in the transaction header, the entire
transaction packets are forwarded to the destination VPPB for formatting as a serial-type PCIe packet through the
transmit circuits in the data link layer and physical layer. The following sections describe these function elements
for processing PCIe packets within the Switch.
5.1
PHYSICAL LAYER CIRCUIT
The physical layer circuit design is based on the PHY Interface for PCI Express Architecture (PIPE). It contains
Physical Media Attachment (PMA) and Physical Coding Sub-layer (PCS) blocks. PMA includes Serializer/
Deserializer (SERDES), PLL1, Clock Recovery module, receiver detection circuits, electrical idle detector, and
input/output buffers. PCS consists of framer, 8B/10B encoder/decoder, receiver elastic buffer, and PIPE PHY
control/status circuitries. To provide the flexibility for port configuration, each lane has its own control and status
signals for MAC to access individually. In addition, a pair of PRBS generator and checker is included for PHY
built-in self test. The main functions of physical layer circuits include the conversion between serial-link and
parallel bus, provision of clock source for the Switch, resolving clock difference in receiver end, and detection of
physical layer errors.
In order to meet the different application needs, the driving current and equalization of each transmitting channels
can be adjusted using EEPROM individually. The driver current of each channel is set to 20mA in default mode. To
change the current value, the user can program the EEPROM for nominal value (HIDRV, LODRV) or actual value
(DTX [3:0]), which is a scaled multiple of Inom. The following tables illustrate the possible transmitted current
values the chip provides.
Table 5-1 Nominal Driver Current Values (Inom)
HIDRV
LODRV
NOMINAL DRIVER CURENT
0
20 mA
0
1
10 mA
1
0
28 mA
1
Reserved
Table 5-2 Ratio of Actual Current and Nominal Current
DTX [3:0]
ACTUAL CURRENT / NOMINAL CURRENT
0000
1.00
0001
1.05
0010
1.10
0011
1.15
0100
1.20
0101
1.25
0110
1.30
1 Multiple lanes could share the PLL.
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| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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