- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1962 > PI7C9X20303ULAZPE (Pericom)IC PCIE PACKET SWITCH 132TQFN PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 58/77頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)當(dāng)前第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 61 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
6
ECRC Generation
Enable
RWS
When set, it enables the generation of ECRC when needed.
Reset to 0b.
7
ECRC Check
Capable
RO
When set, it indicates the Switch has the capability to check ECRC.
Reset to 1b.
8
ECRC Check Enable
RWS
When set, the function of checking ECRC is enabled.
Reset to 0b.
31:9
Reserved
RO
Reset to 0.
7.2.85
HEADER LOG REGISTER – OFFSET From 11Ch to 128h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
1st DWORD
ROS
Hold the 1st DWORD of TLP Header. The Head byte is in big endian.
63:32
2nd DWORD
ROS
Hold the 2nd DWORD of TLP Header. The Head byte is in big endian.
95:64
3rd DWORD
ROS
Hold the 3rd DWORD of TLP Header. The Head byte is in big endian.
127:96
4th DWORD
ROS
Hold the 4th DWORD of TLP Header. The Head byte is in big endian.
7.2.86
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET
140h (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Extended
Capabilities ID
RO
Read as 0002h to indicate that these are PCI express extended capability
registers for virtual channel.
7.2.87
CAPABILITY VERSION – OFFSET 140h (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
Capability Version
RO
Read as 1h. Indicates PCIe Base Specification compliance.
Reset to 1h.
7.2.88
NEXT ITEM POINTER REGISTER – OFFSET 140h (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:20
Next Capability
Offset
RO
Pointer points to the PCI Express Power Budgeting Capability register
(20Ch).
Reset to 20Ch.
7.2.89
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
2:0
Extended VC Count
RO
It indicates the number of extended Virtual Channels in addition to the default
VC supported by the Switch.
Reset to 000b.
3
Reserved
RO
Reset to 0b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X20404GPBNBE | IC PCIE PACKET SWITCH 148LFBGA |
| PI7C9X20404SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20505GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X20508GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X440SLBFDE | IC PCIE-TO-USB 2.0 CTRLR 128LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404GPANBE | 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays |
| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。