TM Family Datasheet Page 3 of 77 August 2009 – Rev" />
參數(shù)資料
型號: PI7C9X20303ULAZPE
廠商: Pericom
文件頁數(shù): 23/77頁
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝: 168
系列: UltraLo™
應(yīng)用: 封裝開關(guān),3 端口/3 線道
接口: PCI Express
封裝/外殼: 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝: 132-TQFN-EP(10x10)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 3 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
REVISION HISTORY
Date
Revision Number
Description
11/27/08
0.0
Preliminary datasheet drafted
2/26/08
0.1
Corrected Chapter 5 Functional Description (multiple virtual channels)
Updated Chapter 6 EEPROM (0Ch)
Updated Chapter 6 EEPROM (A0h, A2h, A4h)
Modified Chapter 7 Registers (7.2.2 Device ID Register, 7.2.50 Replay
Time-Out Counter Bit[13:15], 7.2.52 Switch Operation Mode Bit[14:15],
7.2.64 PCI Express Capability Bit[24], 7.2.70 Link Status Bit[28], 7.2.99
Power Budgeting Data, 7.2.100 Power Budget Capability)
Updated 9.5 JTAG Boundary Scan Register Order
Updated Chapter 3.5 Power Pins (VDDC, VDDA, VDDAUX)
Updated Chapter 6 EEPROM (A0h, A2h, A4h)
Updated Chapter 1 Features (Power Dissipation)
Updated Chapter 11.1 AC Specification (VDDAUX)
Updated Chapter 11.2 DC Specification (Power Consumption, VDDAUX)
Updated Chapter 10 Power Management (VDDAUX)
Updated Figure 12-1 Package outline drawing (Revision B)
Corrected 3.1 PCI EXPRESS INTERFACE SIGNALS (DWNRST_L), 3.3
MISCELLANEOUS SIGNALS (PORTERR, MRL_PDC, NC)
Updated 4.1 PIN LIST of 132-PIN TQFN (A30, B5, B46)
Modified 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION
REGISTERS (0Ch: B0h, 0Eh: Revision ID)
Corrected 7.2.52 Switch Operation Mode (Upstream Port) Bit[16:31],
Corrected 7.2.53 Switch Operation Mode (Downstream Port) Bit[16:31]
5/20/08
0.2
Updated 1 Features (typical latency, removed peer-to-peer switching, power
consumption)
Updated Chapter 3.1 PCI Express Interface Signals (REFCLKP,
REFCLKN)
Updated Chapter 3.3 Miscellaneous Signals (MRL_PDC to PRSNT)
Updated 3.2 Port Configuration Signals (SLOT_IMP, MRL_PDC)
Updated 4.1 Pin-List
Modified 5.1 Physical Layer Circuit
Updated Chapter 6.1.3 EEPROM Space Address Map (10h to 14h, 50h to
54h)
Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers
(0Ch: Ordering Frozen, TX SOF Latency, Surprise Down Capability Enable,
Power Management Data Select, 20h, 22h, 24h: Removed LPVC, Added
PMCSR, 51h, 52h, 53h, 54h, 55h, 56h)
Updated Chapter 7.2 Transparent Mode Configuration Registers (A4h, B4h,
B8, BCh, C0h, C4h)
Updated 7.2.5 Revision ID Register, 7.2.27 Interrupt Pin Register, 7.2.32
Power Management Data Register Bit[3], 7.2.46 Next Item Pointer Register,
7.2.50 Replay Time-Out Counter, 7.2.51 Acknowledge Latency Timer,
7.5.52 Switch Operation Mode, 7.2.53 Switch Operation Mode
(Downstream Port) Bit[16:31], 7.2.54 XPIP CSR2, 7.2.55 SSID/SSVID
Capability ID Register, 7.2.56 Next Item Pointer Register, 7.2.57 Subsystem
Vendor ID Register, 7.2.58 Subsystem ID Register, 7.2.65 PCI Express
Capabilities Register Bit[19:16], 7.2.69 Link Capabilities Register Bit 19,
7.2.86 Capability Version Bit[19:16], 7.2.93 VC Resource Control Register
Bit [26:24], 7.2.97 Capability Version Bit[19:16]
Updated 9.5 JTAG Boundary Scan Register Order
Added Chapter 11.2 Power Consumption
Corrected Chapter 11.3 DC Specifications
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