TM Family Datasheet Page 19 of 77 August 2009 – Re" />
參數(shù)資料
型號： PI7C9X20303ULAZPE
廠商： Pericom
文件頁數(shù)： 11/77頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標準包裝： 168
系列： UltraLo™
應用： 封裝開關，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤
供應商設備封裝： 132-TQFN-EP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 19 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
5.5
TC/VC MAPPING
The 3-bit TC field defined in the header identifies the traffic class of the incoming packets. To enable the
differential service, a TC/VC mapping table at destination port that is pre-programmed by system software or
EEPROM pre-load is utilized to cast the TC labeled packets into the desired virtual channel. Note that all the traffic
classes are mapped to VC0, since only VC0 is available on the Switch. After the TC/VC mapping, the receive block
dispatches the incoming request, completion, or data into the VC0 queues.
5.6
QUEUE
In PCI Express, it defines six different packet types to represent request, completion, and data. They are respectively
Posted Request Header (PH), Posted Request Data payload (PD), Non-Posted Request Header (NPH), Non-Posted
Data Payload (NPD), Completion Header (CPLH) and Completion Data payload (CPLD). Each packet with
different type would be put into a separate queue in order to facilitate the following ordering processor. Since NPD
usually contains one DW, it can be merged with the corresponding NPH into a common queue named NPHD.
5.6.1
PH
PH queue provides TLP header spaces for posted memory writes and various message request headers. Each header
space occupies sixteen bytes to accommodate 3 DW or 4 DW headers.
5.6.2
PD
PD queue is used for storing posted request data. If the received TLP is of the posted request type and is determined
to have payload coming with the header, the payload data would be put into PD queue.
5.6.3 NPHD
NPHD queue provides TLP header spaces for non-posted request packets, which include memory read, IO read, IO
write, configuration read, and configuration write. Each header space takes twenty bytes to accommodate a 3-DW
header, s 4-DW header, s 3-WD header with 1-DW data, and a 4-DW header with 1-DW data.
5.6.4 CPLH
CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to
accommodate a 3-DW header. Please note that there is no 4-DW completion headers.
5.6.5 CPLD
CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to
have payload coming with the header, the payload data would be put into CPLD queue.
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相關代理商/技術參數(shù)
參數(shù)描述
PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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