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參數(shù)資料
| 型號： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 18/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 25 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
ADDRESS
PCI CFG OFFSET
DESCRIPTION
BCh: Bit[0]
ECh(port0~2)
ECh : Bit [19]
BCh(Port 0~2)
BCh: Bit[1]
BCh(Port 0~2)
BCh: Bit[2]
BCh(Port 0~2)
BCh: Bit[3]
Bit [11]: Set to zero to shorten latency
Surprise Down Capability Enable for Port 0~2
Bit [12]: Enable Surprise Down Capability
Power Management’s Data Select Register R/W Capability for Port 0~2
Bit [13]: Enable Data Select Register R/W
Flow Control Update Type for Port 0~2
Bit [14]: Select Flow Control Update Type
4KB Boundary Check Enable
Bit [15]: Enable 4KB Boundary Check
0Eh
08h: Bit[7:0]
Revision ID
Bit [7:0]: Indicates the Revision ID of chip.
10h
B8h (port 0)
B8h : Bit[7:0]
A8h(Port 0)
A8h: Bit [14:13]
B8h (port0)
B8h : Bit[11:10]
B8h : Bit[12]
FTS Number for Port 0
Bit [7:0]: FTS number at receiver side
RefClk ppm Difference for Port 0
Bit [9:8]: It represents RefClk ppm difference between the two
ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300
ppm
Scrambler Control for Port 0
Bit [11:10]: scrambler control
Bit [12]: L0s
12h
B8h (port 1)
B8h : Bit[7:0]
A8h(Port 1)
A8h: Bit [14:13]
B8h (port1)
B8h : Bit[11:10]
B8h : Bit[12]
FTS Number for Port 1
Bit [7:0]: FTS number at receiver side
RefClk ppm Difference for Port 1
Bit [9:8]: It represents RefClk ppm difference between the two
ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300
ppm
Scrambler Control for Port 1
Bit [11:10]: scrambler control
Bit [12]: L0s
14h
B8h (port 2)
B8h : Bit[7:0]
A8h(Port 2)
A8h: Bit [14:13]
B8h (port2)
B8h : Bit[11:10]
B8h : Bit[12]
FTS Number for Port 2
Bit [7:0]: FTS number at receiver side
RefClk ppm Difference for Port 2
Bit [9:8]: It represents RefClk ppm difference between the two
ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300
ppm
Scrambler Control for Port 2
Bit [11:10]: scrambler control
Bit [12]: L0s
F0h (Port 0)
F0h: Bit [28]
80h (Port 0)
80h: Bit[21]
ECh (Port 0)
ECh: Bit [25:24]
84h (Port 0)
84h: Bit [14:13]
Slot Clock Configuration for Port 0
Bit [1]: When set, the component uses the clock provided on the
connector
Device specific Initialization for Port 0
Bit [2]: When set, the DSI is required
Port Number for Port 0
Bit [5:4]: It represents the logic port numbering for physical port
0
PMCSR Data Scale for Port 0
Bit [7:6]: It represents the PMCSR Data Scale for physical port 0
20h
154h (Port 0)
154h: Bit [7:1]
VC0 TC/VC Map for Port 0
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404GPANBE | 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays |
| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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