- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1962 > PI7C9X20303ULAZPE (Pericom)IC PCIE PACKET SWITCH 132TQFN PDF資料下載
參數(shù)資料
| 型號： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 5/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 13 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
NAME
PIN
TYPE
DESCRIPTION
PRSNT [2:1]
A5, A71
I
Present: When asserted low, it represents the device is present in the
slot of downstream ports. Otherwise, it represents the absence of the
device. PRSNT [x] is correspondent to Port x, where x=1,2. The pins
have internal pull-down.
GPIO [7:0]
B13, A15,
B12, A14,
B11, A13,
A12, B10
I/O
General Purpose Input and Output: These eight general-purpose
pins are programmed as either input-only or bi-directional pins by
writing the GPIO output enable control register.
When SMBus is implemented, GPIO[7:5] act as the SMBus address
pins, which set Bit 2 to 0 of the SMBus address.
PWR_SAV
A10
I
Power Saving Mode: PWR_SAV is a strapping pin. When this pin is
pulled high when system is reset, the Power Saving Mode is enabled.
When this pin is pulled low when system is reset, the Power Saving
Mode is disabled. When this pin is pulled low, it should be tied to
ground through a pull-down resistor. When this pin is pulled high, a
pull-up resistor should be used. The suggested value for the pull-up and
pull-down resistor is 5.1K. Pin has an internal pull-down.
P0_CTCDIS
P1_CTCDIS
P2_CTCDIS
B9
B15
A18
I
P0/P1/P2 CTC Disable: These pins should be tied to ground through a
pull-down resistor. The suggested value for the pull-down resistor is
5.1K. The pins have internal pull-down.
TEST1/3/4/5/6/7
A17, A8, B6,
A7, A70, B18
I
Test1/3/4/5/6/7: These pins are for internal test purpose.
Test1/3/4/5/6/7 should be tied to ground through a pull-down resistor.
The suggested value for the pull-down resistor is 5.1K.
TEST2
A38
I
Test2: This pin is for internal test purpose.
Test2 should be tied to 3.3V through a pull-up resistor. The suggested
value for the pull-up resistor is 5.1K.
NC
A1, A2, A3,
A16, A19,
A20, A24,
A30, A35,
A36, A37,
A39, A40,
A42, A46,
A48, A49,
A50, A53,
A54, A55,
A56, A59,
A72, B4, B5,
B28, B33,
B34, B39,
B40, B46
Not Connected: These pins can be left floating.
3.4
JTAG BOUNDARY SCAN SIGNALS
NAME
PIN
TYPE
DESCRIPTION
TCK
B27
I
Test Clock: Used to clock state information and data into and out of
the chip during boundary scan. When JTAG boundary scan function is
not implemented, this pin should be left open (NC).
TMS
A34
I
Test Mode Select: Used to control the state of the Test Access Port
controller. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be pulled low through a
5.1K pull-down resistor.
TDO
A32
O
Test Data Output: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data out of the Test Access Port (TAP) in a serial bit
stream. When JTAG boundary scan function is not implemented, this
pin should be left open (NC).
TDI
B29
I
Test Data Input: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data and instructions into the TAP in a serial bit
stream. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be left open (NC).
TRST_L
B31
I
Test Reset (Active LOW): Active LOW signal to reset the TAP
controller into an initialized state. The pin has internal pull-up. When
JTAG boundary scan function is not implemented, this pin should be
pulled low through a 5.1K pull-down resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X20404GPBNBE | IC PCIE PACKET SWITCH 148LFBGA |
| PI7C9X20404SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20505GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X20508GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X440SLBFDE | IC PCIE-TO-USB 2.0 CTRLR 128LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404GPANBE | 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays |
| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。