TM Family Datasheet Page 24 of 77 August 2009 – Re" />
參數(shù)資料
型號(hào)： PI7C9X20303ULAZPE
廠商： Pericom
文件頁數(shù)： 17/77頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝： 168
系列： UltraLo™
應(yīng)用： 封裝開關(guān)，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝： 132-TQFN-EP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 24 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
15 – 8
7 – 0
BYTE OFFSET
Reserved
96h
Reserved
98h
Reserved
9Ah
Reserved
9Ch
Reserved
9Eh
Reserved
PM Control Para/Rx Polarity for Port 0
A0h
Reserved
PM Control Para/Rx Polarity for Port 1
A2h
Reserved
PM Control Para/Rx Polarity for Port 2
A4h
Reserved
A6h
6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS
ADDRESS
PCI CFG OFFSET
DESCRIPTION
00h
EEPROM signature – 1516h
02h
00h ~ 01h
Vendor ID
04h
02h ~ 03h
Device ID
06h
144h (Port 0~2)
144h: Bit [0]
ECh (Port 0~2)
ECh: Bit [14:12]
ECh: Bit [17:15]
B4h (Port 0~2)
B4h:Bit [5]
Bit [6]
Bit [0]
Bit [2:1]
Bit [3]
Bit [4]
3Ch (Port 1~2)
3Ch: Bit [8]]
Extended VC Count for Port 0 ~ 2
Bit [0]: It represents the supported VC count other than the
default VC
Link Capability for Port 0 ~ 2
Bit [3:1]: It represents L0s Exit Latency for all ports
Bit [6:4]: It represents L1 Exit Latency for all ports
Switch Mode Operation for Port 0
Bit [8]: no ordering on packets for different egress port mode
Bit [9]: no ordering on different tag of completion mode
Bit [10]: Store and Forward
Bit [12:11]: Cut-through Threshold
Bit [13] : Port arbitrator Mode
Bit [14]: Credit Update Mode
Interrupt pin for Port 1 ~ 2
Bit [15]: Set when INTA is requested for interrupt resource
08h
C4h: Bit [15:0]
Subsystem Vender ID
0Ah
C4h: Bit [31:16]
Subsystem ID
0Ch
E4h(Port 0~2)
E4h: Bit 0
ECh(Port 0~2)
ECh: Bit[11:10]
E4h(Port 0~2)
E4h: Bit[15]
B0h(port 0~2)
B0h : Bit [14]
B0h(port 0~2)
B0h : Bit [15]
B4h(port 0~2)
B4h : Bit [15]
B0h(port 0~2)
B0h : Bit [13]
B4h(Port 0~2)
B4h: Bit [7]
BCh(Port 0~2)
Max_Payload_Size Support for Port 0 ~ 2
Bit [0]: Indicated the maximum payload size that the device can
support for the TLP
ASPM Support for Port 0 ~ 2
Bit [2:1] : Indicate the level of ASPM supported on the PCIe link
Role_Base Error Reporting for Port 0 ~ 2
Bit [3] : Indicate implement the role-base error reporting
MSI Capability Disable for Port 0~2
Bit [4] : Disable MSI capability
AER Capability Disable for Port 0~2
Bit [5] : Disable AER capability
Compliance Pattern Parity Control Disable for Port 0~2
Bit [6] : Disable compliance pattern parity
Power Management Capability Disable for Port 0~2
Bit [7] : Disable Power Management Capability
Ordering Frozen for Port 0~2
Bit [10]: Freeze the ordering feature
TX SOF Latency Mode for Port 0~2
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參數(shù)描述
PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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