參數(shù)資料
型號(hào)： PH28F128W18BD60A
廠商： INTEL CORP
元件分類： PROM
英文描述： 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56
封裝： 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56
文件頁(yè)數(shù)： 90/106頁(yè)
文件大小： 1496K
代理商： PH28F128W18BD60A
Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
84
Order Number: 290701, Revision: 015
14.0
Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The Read Configuration Register data
is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set Read
Configuration Register command is written along with the configuration data (on the address bus).
This is followed by a second write that confirms the operation and again presents the Read
Configuration Register data on the address bus. The Read Configuration Register data is latched on
the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions
independently of the applied VPP voltage. After executing this command, the device returns to
read-array mode. The Read Configuration Register’s contents can be examined by writing the Read
Identifier command and then reading location 05h. See Table 27 and Table 28.
Table 27.
Read Configuration Register Summary
Re
a
d
M
o
d
e
Re
s
’d
First Access
Latency Count
W
A
IT
P
o
la
ri
ty
Da
ta
O
u
tp
u
t
Co
n
fi
g
W
A
IT
C
o
n
fig
Bu
rs
tS
e
q
C
loc
k
C
onf
ig
Re
s
’d
Re
s
’d
Bu
rs
tW
ra
p
Burst Length
RM
R
LC2
LC1
LC0
WT
DOC
WC
BS
CC
R
BW
BL2
BL1
BL0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 28.
Read Configuration Register Descriptions (Sheet 1 of 2)
Bit
Name
Description
1
Notes
15
RM
Read Mode
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
2
14
R
Reserved
5
13-11
LC[2:0]
First Access Latency
Count
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
6
10
WT
WAIT Signal Polarity
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
3
9
DOC
Data Output
Configuration
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
6
8
WC
WAIT Configuration
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
6
7
BS
Burst Sequence
1 = Linear Burst Order (Default)
6
CC
Clock
Configuration
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
(Default)
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