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參數(shù)資料
| 型號(hào)： | PH28F128W18BD60A |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封裝： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件頁數(shù)： | 79/106頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
74
Order Number: 290701, Revision: 015
After writing the Erase Confirm command, the selected partition is placed in read Status Register
mode and reads performed to that partition return the current status data. The address given during
the Erase Confirm command does not need to be the same address used in the Erase Setup
command. So, if the Erase Confirm command is given to partition B, then the selected block in
partition B will be erased even if the Erase Setup command was to partition A.
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, an Erase
Setup command must be immediately followed by the Erase Confirm command in order to execute
properly. If a different command is issued between the setup and confirm commands, the partition
is placed in read-status mode, the Status Register signals a command sequence error, and all
subsequent erase commands to that partition are ignored until the Status Register is cleared.
The CPU can detect block erase completion by analyzing SR[7] of that partition. If an error bit
(SR[5,3,1]) was flagged, the Status Register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition remains in read-status mode until
another command is written to its CUI. Any CUI instruction can follow after erasing completes.
The CUI can be set to read-array mode to prevent inadvertent Status Register reads.
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