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參數(shù)資料
| 型號： | PH28F128W18BD60A |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封裝： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件頁數(shù)： | 64/106頁 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
60
Order Number: 290701, Revision: 015
10.0
Read Operations
The device supports two read modes - asynchronous page and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register (RCR) must be configured to enable synchronous burst reads of the flash
memory array (see Section 14.0, “Set Read Configuration Register” on page 84).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or CFI Query. Upon power-up, or after a reset, all partitions of the device default to the Read
Array state. To change a partition’s read state, the appropriate read command must be written to the
device (see Section 9.2, “Device Commands” on page 55).
The following sections describe device read modes and read states in detail.
10.1
Asynchronous Page Read Mode
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 14.0, “Set Read Configuration Register” on page 84).
To perform an asynchronous page mode read, an address is driven onto A[MAX:0], and CE#, OE#
and ADV# are asserted. WE# and RST# must be deasserted. WAIT is asserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2
Synchronous Burst Read Mode
To perform a synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and
OE# are asserted. WE# and RST# must be deasserted. ADV# is asserted, and then deasserted to
latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which
case the address is latched on the next valid CLK edge after ADV# is asserted. See Section 14.0,
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see Section 14.2, “First Access
Latency Count (RCR[13:11])” on page 86). Subsequent data is output on valid CLK edges
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