參數(shù)資料
型號(hào)： PH28F128W18BD60A
廠商： INTEL CORP
元件分類： PROM
英文描述： 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56
封裝： 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56
文件頁(yè)數(shù)： 43/106頁(yè)
文件大?。?/td> 1496K
代理商： PH28F128W18BD60A
Intel
Wireless Flash Memory (W18)
Datasheet
Intel Wireless Flash Memory (W18)
07-Dec-2005
Order Number: 290701, Revision: 015
41
7.1
AC Write Characteristics
Table 13.
AC Write Characteristics - 90 nm Lithography
#
Sym
Parameter (1,2)
VCCQ =
1.70 V – 1.95 V
Unit
Notes
Min
Max
W1
tPHWL (tPHEL)
RST# High Recovery to WE# (CE#) Low
150
-
ns
W2
tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Low
0
-
ns
W3
tWLWH (tELEH)
WE# (CE#) Write Pulse Width Low
40
-
ns
W4
tDVWH (tDVEH)
Data Setup to WE# (CE#) High
40
-
ns
W5
tAVWH (tAVEH)
Address Setup to WE# (CE#) High
40
-
ns
W6
tWHEH (tEHWH)
CE# (WE#) Hold from WE# (CE#) High
0
-
ns
W7
tWHDX (tEHDX)
Data Hold from WE# (CE#) High
0
-
ns
W8
tWHAX (tEHAX)
Address Hold from WE# (CE#) High
0
-
ns
W9
tWHWL (tEHEL)
WE# (CE#) Pulse Width High
20
-
ns
W10
tVPWH (tVPEH)
VPP Setup to WE# (CE#) High
200
-
ns
W11
tQVVL
VPP Hold from Valid SRD
0
-
ns
W12
tQVBL
WP# Hold from Valid SRD
0
-
ns
W13
tBHWH (tBHEH)
WP# Setup to WE# (CE#) High
200
-
ns
W14
tWHGL (tEHGL)
Write Recovery before Read
0
-
ns
W16
tWHQV
WE# High to Valid Data
t
AVQV
+20
-ns
3,6,10
W18
tWHAV
WE# High to Address Valid
0
-
ns
3,9,10
W19
tWHCV
WE# High to CLK Valid
12
-
ns
3,10
W20
tWHVH
WE# High to ADV# High
12
-
ns
3,10
W21
tVHWL
ADV# High to WE# Low
<21
ns
11
W22
tCHWL
CLK to WE# Low
<21
ns
11
W27
tWHEL
WE# High to CE# Low
0
W28
tWHVL
WE# High to ADV# Low
0
Notes:
1.
Write timing characteristics during erase suspend are the same as during write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or
WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE#
low (whichever is last). Hence, tWLWH = tEHEL = tWHEL = tEHWL.
6.
System designers should take this into account and may insert a software No-Op instruction to delay the first
read after issuing a command.
7.
For commands other than resume commands.
8.
VPP should be held at VPP1 or VPP2 until block erase or program success is determined.
9.
Applicable during asynchronous reads following a write.
10.
tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and
tWHVH both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge,
whichever occurs first).
11.
The specifications tVHWL and tCHWL can be ignored if there is no clock toggling during the write bus cycle.
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