參數(shù)資料
型號: PDI1394L41
廠商: NXP Semiconductors N.V.
英文描述: Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器)
中文描述: 影音內(nèi)容保護(hù)鏈路層(內(nèi)容可保護(hù)的視聽鏈接層控制器)
文件頁數(shù): 7/81頁
文件大?。?/td> 303K
代理商: PDI1394L41
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Apr 15
4
8.0
APPLICATION DIAGRAM
MPEG OR DVC
DECODER
PDI1394L41
AV LINK
AV
INTERFACE
PDI1394Pxx
PHY
PHY–LINK
INTERFACE
HOST CONTROLLER
DATA 16/
ADDRESS 9/
INTERRUPT & CONTROL
1394 CABLE
INTERFACE
MPEG OR DVC
DECODER
AV
INTERFACE
SV01023
9.0
PIN DESCRIPTION
9.1
Host Interface
PIN No.
13, 14, 15, 16, 19,
20, 21, 22
1, 2, 3, 4, 7, 8, 9,
10
26, 27, 28, 29, 30,
31, 32, 33
PIN SYMBOL
I/O
NAME AND FUNCTION
HIF AD[7:0]
I/O
Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
HIF D[15:8]
I/O
Host Interface Data 15 (MSB) through 8. Only used in 16 bit access mode (HIF
16BIT = HIGH).
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules (Section 12.5).
Control bit used to indicate the first byte/word of a read function or the last byte/word of a write
function so that the data quadlet is fetched or stored. See Section 12.5 for more information
regarding the host interface.
HIF A[7:0]
I/O
25
HIF A8
I
36
HIF CSN
I
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control
and status registers.
Write enable. When asserted (LOW) in conjunction with HIF CSN, a write to the PDI1394L41
internal registers is requested. (NOTE: HIF WRN and HIF RDN : if these are both LOW in
conjunction with HIF CSN, then a write cycle takes place. This can be used to connect CPUs
that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the
R/W_N line to the HIF WRN and tie HIF RDN LOW.)
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L41. Read the General
Interrupt Register for more information. This pin is open drain and requires a 1K pull-up
resistor.
37
HIF WRN
I
38
HIF INTN
O
39
HIF ALE
I
Address latch enable. Used in multiplex mode only.
Read enable. When asserted (LOW) in conjunction with HIF CSN, a read of the PDI1394L41
internal registers is requested.
Wait signal. Signals Host interface in WAIT condition when HI. See Section 12.5.
Reset (active LOW). The asynchronous master reset to the PDI1394L41.
Host interface mode pin. When LOW HIF operates in 8 bit mode. When HIGH HIF operates in
16 bit mode.
Host interface mode pin. When LOW HIF operates in non-multiplex mode, when HIGH HIF
operates in multiplex mode. When HIGH, the low-order eight address bits are multiplexed with
data on HIF AD[7:0], otherwise they are non-multiplexed and supplied on A[7:0].
40
HIF RDN
I
41
42
HIF WAIT
RESETN
O
I
45
HIF 16BIT
I
46
HIF MUX
I
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