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參數(shù)資料
| 型號： | PDI1394L41 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Content Protection AV Link Layer(內(nèi)容可保護的AV鏈接層控制器) |
| 中文描述： | 影音內(nèi)容保護鏈路層（內(nèi)容可保護的視聽鏈接層控制器） |
| 文件頁數(shù)： | 14/81頁 |
| 文件大?。?/td> | 303K |
| 代理商： | PDI1394L41 |
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Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Apr 15
11
12.2.5
The AV transmitter has some additional features to support mLAN (IEC 61883-6). These are enabled by setting bit 30 of ITXPKCTL (0x020) to
logic 1. At the rising edge of AVxFSYNC, a SYT time stamp will be generated and written into the SYT queue of the isochronous transmitter.
This stamp will point to a time in the future dictated by the following formula:
mLAN Support
SYT[15:12] = CYCTM[15:12] + programmed SYT_DELAY value + 2
SYT[11:0] = CYCTM[11:0]
The additional delay of two cycles is specific to this mLAN mode. The oldest SYT time stamp in the SYT queue will be sent first, but only when
accompanied by a data payload. Any pending SYT time stamp will be held until the next non-empty bus packet is sent. At the moment of
transmission, the SYT time stamp should at least point one cycle in the future. If it points to a time that is less than one cycle in the future, it will
be discarded.
The SYT queue in the isochronous transmitter can store 4 entries, the SYT queue in the isochronous receiver can store six entries. This
supports the case where an 8 kHz signal is applied to AVxFSYNC, and mLAN = 1, and SYT_Delay = 2. Assuming there is data on every cycle,
the receiver will receive an SYT time stamp each cycle with the first SYT time stamp pointing just less than six cycles in the future. When the
SYT queue in the isochronous receiver is full, then the most recently received SYT time stamp is overwritten with the next arriving SYT time
stamp.
12.2.6
This feature supports the 1394 digital camera specification. The state of this pin will be reflected in the SY bit (ITXCTL register 0x034) and will
be transmitted along with the isochronous data block that was entered with it. The intended use of this pin is to signal the start of a new frame of
video in the isochronous header section of the data payload. Similarly, the isochronous receiver will assert the AVxSY pin simultaneously with
the first byte of the isochronous bus packet in which the SY value was received.
NOTE:
The SY functionality is only intended to be used when
the M6 cipher and de-cipher are not enabled.
SY – Sync Support
SV01787
AV DATA
AV SYNC
AV SY
Figure 1.
Behavior of sysncr
12.2.7
The PDI1394L41 maintains six distinct buffers that are highly configurable to optimize bandwidth capabilities. Buffers can be increased or
decreased from the default value by accessing the indirect address range of 0x100 through 0x1FC (INDADDR, 0x0F8). If the AV Layer is
configured to transmit or receive DVB compliant MPEG-2 type data, the default Isochronous (AV) buffer sizes are recommended. FIFO sizes
cannot be changed dynamically; after a FIFO size change, transmitters and receivers must be reset.
Programmable Buffer Memory
Buffers can be programmed with 64 quadlet (256 Byte) granularity. Minimum buffer size is 64 quadlets, maximum buffer size is limited to 11 kB.
The sum of all buffers cannot exceed 12K Bytes, or 3K Quadlets.
DEFAULT BUFFER SIZE
BUFFER MEMORY
SIZE
(Quadlets)
256
Asynchronous Receive Response FIFO
Asynchronous Receive Request FIFO
256
Asynchronous Transmit Response FIFO
256
Asynchronous Transmit Request FIFO
256
Isochronous (AV) Transmit Buffer
1024
Isochronous (AV) Receive Buffer
1024
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相關(guān)代理商/技術(shù)參數(shù) |
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| PDI1394L41BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 content protection AV link layer controller |
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| PDI1394P11A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11ABD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11ABD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
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