參數(shù)資料
型號: PDI1394L41
廠商: NXP Semiconductors N.V.
英文描述: Content Protection AV Link Layer(內(nèi)容可保護的AV鏈接層控制器)
中文描述: 影音內(nèi)容保護鏈路層(內(nèi)容可保護的視聽鏈接層控制器)
文件頁數(shù): 44/81頁
文件大?。?/td> 303K
代理商: PDI1394L41
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Apr 15
41
12.7.1.1
Interrupt Hierarchy
10
18 17 16 15 14 13
9 8 7
A
6
5 4 3
2 1
0
SV00913
7
6
5 4 3
2 1
C
0
3
2 1
0
L
ITXINTACK (0x02C)
IRXINTACK (0x04C)
ASYINTACK (0x0A0)
LNKPHYINTACK (0x008)
GLOBCSR (0x018)
HIF INT_N
P
C
F
P
I
P
S
H
A
C
T
C
C
C
C
C
I
T
T
D
I
I
D
S
I
C
R
F
S
A
I
I
16 15 14 13 12 11 10 9 8
7
6
5 4
3
T
2 1
T
0
T
R
R
R
R
R
R
R
S
R
T
R
T
T
T
6
5 4 3
2 1
0
I
8
I
9
7
I
I
8
I
I
9
20
T
12
I
13
I
21
A
12
I
13
I
10
I
14
M
Figure 33.
Interrupt Hierarchy
13.0
Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the
lower 8 bits, and leave the other bits unaffected (see Section 12.5.2 for more information). The values written to undefined fields/bits are ignored
and thus DON’T CARE.
REGISTER MAP
A full bitmap of all registers is listed in Table 6. The meaning of shading and bit cell values is as follows:
A bit/field with no name written in it and dark shading is reserved and not used.
A bit/field with a name in it and light shading is a READ ONLY (status) bit/field.
A one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset.
Table 6.
Full Bitmap of all Registers (consists of four tables shown on the following pages)
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