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| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大小： | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 42
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
15.13 DMA Status Register ‘DMS’
The DMS register is located at offset 0x11 of the ICR. This
allows the internal TXRDY#and RXRDY#lines to be
permanently deasserted, and the current internal status to
be monitored. This mainly has applications for testing.
DMS[0]: RxRdy Status
Read Only: set when RxRdy is asserted (pin driven low).
DMS[1]: TxRdy Status
Read Only: set when TxRdy is asserted (pin driven low).
DMS[5:2] Reserved
DMS[6]: Force RxRdy Inactive
logic 0
RxRdy#acts normally
logic 1
RxRdy#is permanently inactive (high)
regardless of FIFO thresholds
DMA[7]: Force TxRdy Inactive
logic 0
TxRdy#acts normally
logic 1
TxRdy#is permanently inactive (high)
regardless of FIFO thresholds.
15.14 Port Index Register ‘PIX’
The PIX register is located at offset 0x12 of the ICR. This
read-only register gives the UART index. This returns 0, 1,
2 or 3 depending on which UART is being accessed.
15.15 Clock Alteration Register ‘CKA’
The CKA register is located at offset 0x13 of the ICR. This
register adds additional clock control mainly for
isochronous and embedded applications. The register is
effectively an enhancement to the CKS register.
This register is cleared to 0x00 after a hardware reset to
maintain compatibility with 16C550, but is unaffected by
software reset. This allows the user to select a clock mode
and then reset the channel to work-around any timng
glitches.
CKA[0]: Invert Receiver Clock
logic 0
receiver clock as normal
logic 1
receiver clock inverted (isoc apps)
CKA[1]: Invert Transmitter Clock
logic 0
transmtter clock as normal
logic 1
transmtter clock inverted (isoc apps)
CKA[2]: Invert DTR output
logic 0
DTR as normal
logic 1
DTR inverted
CKA[3]: Use CLKSEL as System Clock
logic 0
XTLI used as systemclock
logic 1
CLKSEL used as systemclock
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