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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 1/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Oxford Semiconductor Ltd.
25 Mlton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141
Oxford Semiconductor 2001
OX16C954 rev B Data Sheet R1.0 – November 2001
Part Nos. OX16C954-PCC60-B / OX16C954_TQC60_B
F
EATURES
Four independent full-duplex asynchronous 16C950
high performance UART channels
128-byte deep FIFO per transmtter and receiver
UARTs fully software compatible with industry
standard 16C55x type UARTs
Pin compatible with TL16C554 and ST16C654
Baud rates up to 15 Mbps in normal mode and
60Mbps in external 1x clock (isochronous) mode
Readable FIFO levels
Flexible clock prescaler from1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff characters, in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmtter
FIFO interrupts and automatic in-band and out-of-
band flow control
Readable in-band and out-of-band flow control status
Programmable special character detection
Infra-red (IrDA) receiver and transmtter option
5, 6, 7, 8 and 9-bits data framng
Detection of bad data in the receiver FIFO
Independent channel reset by software
Transmtter and receiver can be disabled
Transmtter idle interrupt
RS-485 buffer enable signals
Four byte device ID
Sleep mode (low operating current)
Systemclock up to 60 MHz at 5V, 50 MHz at 3.3V
5.0 volt or 3.3v operation*
68pin PLCC and 80pin TQFP package options.
*Only the 80pin TQFP package supports operation at 5v or 3.3v.
R
EV
B E
NHANCEMENTS
The OX16C954B is an enhanced, backward-compatible revision of the OX16C954 rev A. It uses the newer core as in the
OX16C950 rev B. The chief enhancements are as follows –
All known errata fixed
Full TCR range from4-16
Enhanced controls for sleep-mode sensitivity, ability to read FCR and Good Data Status
3.3V operation with 80 pin TQFP
Enhanced isochronous clocking options (optional inversions, DTR/DSR)
Hereafter OX16C954 rev B is simply referred to as OX16C954.
OX16C954 rev B
High Performance Quad UART with 128-byte FIFOs
Intel / Motorola Bus Interface
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