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參數(shù)資料
| 型號(hào)： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁(yè)數(shù)： | 19/54頁(yè) |
| 文件大小： | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 19
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
Register
Name
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
To access these registers LCR must be set to 0xBF
CTS
flow
control
control
detect
EFR
010
R/W
RTS
Flow
Special
char
Enhance
mode
In-band flow control mode
XON1
9-bit mode
XON2
9-bit mode
XOFF1
9-bit mode
XOFF2
9-bit mode
100
R/W
XON Character 1
Special character 1
101
R/W
XON Character 2
Special Character 2
110
R/W
XOFF Character 1
Special character 3
111
R/W
XOFF Character 2
Special character 4
Table 5: 650 Compatible Registers
Register
Name
ASR
1,6,7
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
001
R/W
7
Tx
Idle
FIFO
size
FIFO-
SEL
Special
Char
Detect
DTR
RTS
Remote
Tx
Disabled
Tx
Disabled
RFL
6
011
R
Number of characters in the receiver FIFO
TFL
3,6
100
R
Number of characters in the transmtter FIFO
ICR
3,8,9
101
R/W
Data read/written depends on the value written to the SPR prior to
the access of this register (see
Table 7
)
Table 6: 950 Specific Registers
Register access notes:
Note 1: Requires LCR[7] = 0
Note 2: Requires ACR[7] = 0
Note 3: Requires that last value written to LCR was not 0xBF
Note 4: To read this register ACR[7] must be = 0
Note 5: To read this register ACR[6] must be = 0
Note 6: Requires ACR[7] = 1
Note 7: Only bits 0 and 1 of this register can be written
Note 8: To read this register ACR[6] must be = 1
Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set
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