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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 18/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 18
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
6 R
EGISTER DESCRIPTION TABLES
The UART is accessed through an 8-byte block of I/O space (or through memory space). Since there are more than 8 registers,
the mapping is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM
2. LCR specifies the data format used for both transmtter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmtter and receiver data is not affected. Write the desired LCR value to exit fromthis selection.
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 20.
Register
Name
THR
1
000
W
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data to be transmtted
RHR
1
000
R
Data received
IER
1,2
650/950
Mode
CTS
interrupt
mask
RTS
interrupt
mask
Special
Char.
Detect
Alternate
sleep
mode
THR Trigger
Level
FIFO
Size
Unused
550/750
Mode
001
R/W
Unused
Sleep
mode
Modem
interrupt
mask
Rx Stat
interrupt
mask
THRE
interrupt
mask
RxRDY
interrupt
mask
FCR
3
650 mode
RHR Trigger
Level
RHR Trigger
Level
750 mode
Unused
950 mode
010
W
DMA
Mode /
Tx
Trigger
Enable
Flush
THR
Flush
RHR
Enable
FIFO
ISR
3
010
R
FIFOs
enabled
Interrupt priority
(Enhanced mode)
Interrupt priority
(All modes)
Interrupt
pending
LCR
4
011
R/W
Divisor
latch
access
Tx
break
Force
parity
Odd /
even
parity
Parity
enable
Number
of stop
bits
Data length
MCR
3,4
550/750
Mode
Unused
CTS &
RTS
Flow
Control
650/950
Mode
LSR
3,5
Normal
9-bit data
mode
100
R/W
Baud
prescale
Data
Error
IrDA
mode
XON-Any
Enable
Internal
Loop
Back
OUT2
(interrupt
enable)
OUT1
(not
used)
RTS
DTR
Tx Empty
THR
Empty
Rx
Break
Framng
Error
Parity
Error
9
th
Rx
data bit
Trailing
RI edge
Overrun
Error
RxRDY
101
R
MSR
3
110
R
DCD
RI
DSR
CTS
Delta
DCD
Delta
DSR
Delta
CTS
SPR
3
Normal
9-bit data
mode
Temporary data storage register and
Indexed control register offset value bits
111
R/W
Unused
9
th
Tx
data bit
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
DLL
000
R/W
Divisor latch bits [7:0] (Least significant byte)
DLM
001
R/W
Divisor latch bits [15:8] (Most significant byte)
Table 4: Standard 550 Compatible Registers
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