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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 13/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 13
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
TQFP
Interrupt & DMA Pins Contd.
74
67
34
21
PLCC
Dir
1
Name
Description
55
49
O
O
O
INT[3]
INT[2]
INT[1]
Interrupt pin for Uart channel 3 (Intel Bus mode)
Interrupt pin for Uart channel 2 (Intel Bus mode)
Interrupt pin for Uart channel 1 (Intel Bus mode)
Each of these serial channels have a 3-state interrupt output (enabled by
MCR[3] and INTSEL#pin) which goes active (high) when an interrupt
condition occurs. The interrupt is disabled after a hardware reset.
Interrupt pin for Uart channel 0, in Intel bus mode.
This serial channel has a 3-state interrupt output (enabled by MCR[3] and
INTSEL#pin) which goes active (high) when an interrupt condition occurs.
The interrupt is disabled after a hardware reset.
Device interrupt pin (for all uart channels) in Motorola bus mode.
This pin goes active (low) when the interrupt signal fromany of the 4
channels is asserted. Otherwise it is in the high-impedance state.
27
27
15
15
O
OD
INT0
IRQ#
Mscellaneous Pins
6
65
ID
INTSEL#
Active-low Interrupt enable.
When this pin is left open or connected to GND, the three-state interrupts
that are available on INT[3:0] are enabled according to the setting of
MCR[3]. If this pin is high interrupts are enabled regardless of the state of
MCR[3].
This pin is ignored in Motorola bus mode.
Intel or Motorola bus interface select.
When this pin is tied high or left open, the Intel bus interface is selected.
When this pin is tied low, the Motorola bus interface is selected where
RESET, IOW# CS0# CS1#are CS2#are re-assigned and CS3# IOR#
and INTSEL#are unused. In Motorola mode, all the interrupt lines of the
internal uart channels are wired “OR-ed” onto the IRQ#pin.
In 16C554 this pin is unconnected
.
FIFO SIZE select.
For backward compatibility with 16C554, 16C654 and 16C754 devices the
FIFO depth is 16 when FIFOSEL#is high and 128 when FIFOSEL#is
low. The unlatched state of this pin is readable by software. The FIFO size
may be set to 128 by writing a 1 in FCR[5] when LCR[7] is set or by
putting the device into Enhanced mode, thus overriding the state of the
FIFOSEL#pin. Pin 64 is a VDD in 16C554 and 16C654 devices (PLCC).
3.3v or 5.0v I/O buffer selection.
This pin must be tied according to the voltage supply used to power the
TQFP package option.
For 5v supply voltage : Vdetect must be tied low.
For 3.3v supply voltage : Vdetect must be tied high.
NOTE : The PLCC package option does not bond-out this pin, which is
internally pulled down to gnd. So the PLCC is suitable for 5v operation
only
.
49
31
IU
I/M#
5
64
I
FIFOSEL#
52
No pin
ID
VDETECT
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