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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 11/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 11
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
TQFP
Processor Interface Pins in Motorola Mode (I/M#= ‘0’) Contd.
15 to 11
9 to 7
68 to 66
31
18
I
R/W#
PLCC
Dir
1
Name
Description
5 to 1
I/O
DB[7:0]
Eight-bit 3-state data bus.
Read-not-write signal. This signal should be high during read cycles and
low during write cycles.
Serial Port Pins
72
69
32
29
72
69
32
29
75
66
35
26
53
51
19
17
53
51
19
17
56
48
22
14
O
O
O
O
O
O
O
O
O
O
O
O
SOUT[3]
SOUT[2]
SOUT[1]
SOUT[0]
IrDA_Out[3]
IrDA_Out[2]
IrDA_Out[1]
IrDA_Out[0]
RTS[3]#
RTS[2]#
RTS[1]#
RTS[0]#
Serial data output, Uart 3
Serial data output, Uart 2
Serial data output, Uart 1
Serial data output, Uart 0
UART IrDA data outputs, each Uart, respectively.
Serial data output pins are redefined as IrDA data outputs when MCR[6]
of the corresponding UART channel is set in enhanced mode
Active-low Request-To-Send output, for each uart respectively.
Whenever the automated RTS#flow control is enabled for the
corresponding channel, the RTS#pin is de-asserted and re-asserted if the
receiver FIFO reaches or falls below a pair of programmed flow control
thresholds, respectively. The state is controlled by bit 1 of the MCR.
RTS may also be used as a general-purpose output.
Active-low modem“data-termnal-ready output”, for each uart respectively.
If automated DTR#flow control is enabled for the corresponding UART
channel, the DTR#pin is asserted and deasserted if the receiver FIFO
reaches or falls below the channel’s programmed thresholds, respectively.
The state is set by bit 0 of the MCR.
DTR may also be used as a general
purpose output
.
In RS485 half-duplex mode, the DTR#pin of each UART channel may be
programmed to reflect the state of the channel’s transmtter empty bit (or
its inverse) to automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3])
Transmtter 1x (or baud rate generator output) clock. For isochronous
applications, the 1x (or Nx) transmtter clock may be asserted on the
uart’s DTR#pin (see CKS[5:4]).
Serial data input, UART 3.
Serial data input, UART 2.
Serial data input, UART 1.
Serial data input, UART 0.
UART IrDA data inputs, for each uart respectively.
Serial data input pins redefined as IrDA data inputs when MCR[6] of the
corresponding UART channel is set in enhanced mode
77
64
37
24
77
64
37
24
77
64
37
24
4
57
44
17
4
57
44
17
78
63
38
23
58
46
24
12
58
46
24
12
58
46
24
12
63
41
29
7
63
41
29
7
59
45
25
11
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
DTR[3]#
DTR[2]#
DTR[1]#
DTR[0]#
485_En[3]
485_En[2]
485_En[1]
485_En[0]
TxClkOut[3]
TxClkOut[2]
TxClkOut[1]
TxClkOut[0]
SIN[3]
SIN[2]
SIN[1]
SIN[0]
IrDA_In[0:3]
IrDA_In[0:3]
IrDA_In[0:3]
IrDA_In[0:3]
CTS[3]#
CTS[2]#
CTS[1]#
CTS[0]#
Active-low modem“clear-to-send” input, for each uart respectively.
If automated CTS#flow control is enabled for the corresponding UART
channel, upon deassertion of the CTS#pin, the channel’s transmtter will
complete the current character and enter the idle mode until the CTS#pin
is reasserted. Note: flow control characters are transmtted regardless of
the state of the CTS#pin. The state of this pin is reflected in bit 4 of the
MSR.
It can also be used as a general-purpose input
.
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