參數(shù)資料
型號： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 38/128頁
文件大小： 2450K
代理商： OR3TP12-6BA256
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
38
L Lucent Technologies Inc.
PCI Bus Core Master Controller
Detailed Description
(continued)
Termination
Once initiated, Master write operations will continue on
the PCI bus until either all write data is sent, an abort
occurs (either Master or Target), or the PCI bus’ reset
signal (
rstn
) is asserted. During aborts, the Master
address and write data FIFOs will be cleared, and the
FPGA application will be notified by the assertion of
fpga_msyserror
.
If the Master write transaction is terminated with a retry
or disconnected by the external Target before all data
has been transferred, the Master will initiate another
Master write operation, continuing from that point using
a stored address pointer.
On the Master FIFO interface, the FPGA application
identifies the last data word by asserting
mwlastcycn
.
When this data word is transferred to the PCI bus, the
Master will terminate the PCI transaction normally. The
Master will inform the FPGA application of completion
by deasserting
ma_fulln
.
Reset
The FPGA application can apply a reset signal to place
the Master FIFO interface logic in a known state, which
clears all FIFOs and
mstatecntr
. The reset signal,
mfifoclrn
, is asynchronous and therefore should be
asserted for a minimum of one clock cycle and deas-
serted for a minimum of one clock cycle before continu-
ing. This is not recommended to assert
mfifoclrn
while
a current PCI transaction is in progress (
ma_fulln
asserted), since proper PCI bus termination is not
guaranteed. Only PCI
rstn
will reset the internal Master
PCI state machines, while a PCI transaction is in
progress.
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*