參數(shù)資料
型號(hào)： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 22/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
22
L Lucent Technologies Inc.
Symbol
I/O
Description
Clock
Domain
Master Write Data FIFO Signals
mwlastcycn
O
Master Write Last Data Cycle.
This active-low signal has two functions:
a.
It is asserted low to indicate that the current Master start address word is the
final portion being sent. It can be asserted prior to any address portion being
transferred, indicating to use the previous stored address in the selected
Master holding register.
maenn
must be asserted with
mwlastcycn
during
the final address word.
b.
It is asserted low to indicate that the accompanying Master write data is the
final data for this operation.
mwdataenn
must be asserted with
mwlastcycn
during the final data word.
Master Write FIFO Data Enable.
This active-low signal enables the registering
of data bus
mwdata
(quad-port mode) or
datafmfpga
(dual-port mode) during
Master write operations into the Master write data FIFOs.
mwdataenn
should
not be asserted when the Master write data FIFOs are full, or data may be lost.
Master Write PCI Bus Hold.
For Master write transfers on the PCI bus, this
signal delays the start of the transfer (i.e.,
reqn
asserted) on the PCI bus,
allowing the FPGA application to fill the Master write data FIFO. The transac-
tion will begin when
mwpcihold
is deasserted or the Master write data FIFO
becomes full.
mwpcihold
should be deasserted before
mwlastcycn
is
asserted, and
needs to remain asserted for a minimum of two
pciclk
cycles.
Master Write Data FIFO Almost Full Flag.
This active-low signal indicates
that only four more empty 64-bit locations remain in the Master write data
FIFO.
Master Write Data FIFO Full Flag.
This active-low signal indicates that the
Master write data FIFO is full.
mwdataenn
should never be asserted when
mw_fulln
is active.
fclk
*
mwdataenn
O
fclk
*
mwpcihold
O
pciclk
mw_afulln
I
fclk
*
mw_fulln
I
fclk
*
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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