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| 型號： | OR3TP12-6BA256 |
| 英文描述： | Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 34/128頁 |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA256 |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
34
L Lucent Technologies Inc.
PCI Bus Core Master Controller
Detailed Description
FIFO Interface Overview
The Master FIFO interface consists of two transfer
phases: command/address followed by data. This
sequence must be followed, with the assertion of
mwlastcycn
indicating the completion of each phase.
In both quad- and dual-port modes, the command is
transferred first, followed by address, then data. The
PCI start address and bus command are always pro-
vided by the FPGA application. For Master writes, write
data with byte enables will be provided by the FPGA
application, whereas for reads the Master will receive
its data from the PCI bus and forward on to the FPGA
application. All types of data are transferred on the data
paths defined by the operational mode (dual- or quad-
port).
Master State Counter
The Master FIFO interface provides a state counter,
mstatecntr[3:0]
, that informs the FPGA application of
its current state (Table 12). This state counter deter-
mines what data is expected from the FPGA applica-
tion during the command/address or write data phases,
or what is currently being provided by the Master FIFO
interface during read data phases. This state counter
transitions from one state to another in a predeter-
mined manner. Table 13 through Table 17 detail the
sequencing of the
mstatecntr
and the data transferred
for Master write and read transactions.
The value on bus
mstatecntr
can be used to minimize
FPGA logic or verify proper operation. The data pro-
vided by the Master FIFO interface to the FPGA appli-
cation is accompanied by a value on
mstatecntr[3:0]
,
as shown in Table 12. This value can be directly used
by the FPGA application to determine the proper orien-
tation of the Master read data. This eliminates the need
for logic in the FPGA application for possible data pack-
ing functions. The data required from the FPGA appli-
cation by the Master FIFO interface during the
command/address or write data is also defined by the
value on
mstatecntr
. However, the state counter value
being presented to the FPGA application is in the same
cycle that the data is sent from the FPGA. Here, the
value provided by the Master FIFO interface can be
used to determine the next state, since current data,
phase, enables, and state transitions is known.
Dual-Master Address Holding Registers
The Master FIFO interface utilizes a pair of 64-bit
address holding registers to reduce latency when set-
ting up repeated Master transfers to or from the same
PCI address. Every Master command/address phase
has associated with it one of the two holding registers,
as specified by the holding register selector (Master
command word bit 12, as described in Table 10). Each
address holding register records the full previous
address, allowing some, all, or none of that recorded
address to be used to build the next address associ-
ated with that holding register. This can save up to 2/4
cycles (for dual-port/quad-port mode, respectively) dur-
ing the command/address phase.
The holding register supplies the most significant por-
tion, or all, or none, of the address. The amount sup-
plied by the holding register is determined by the timing
of the signal
mwlastcycn
, which accompanies the last
portion of data during the command/address phase. If
mwlastcycn
accompanies the Master command word,
the holding register supplies the entire address. Table
11 gives examples of typical operation using the hold-
ing registers, illustrating the above rules.
The holding registers can be partitioned using one
each for read and write operations, thus providing two
unrelated addresses for two functions. Another useful
application is to dedicate one holding register to a fixed
address such as the beginning of a buffer, the data port
of a FIFO or a mailbox register. This increases effective
bandwidth on shorter bursts.
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PDF描述 |
|---|---|
| OR3TP12-6BA256I | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE |
| OR3TP12-6BA352 | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA256-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BA256I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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