參數(shù)資料
型號(hào)： OR3TP12-6BA256
英文描述： Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 16/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
16
L Lucent Technologies Inc.
PCI Bus Core Detailed Description
(continued)
PCI Protocol Fundamentals
Basic Transfer Control
The following paragraphs describe various aspects of
the PCI protocol and the way they are handled by the
PCI bus core.
Addressing.
The PCI Specification defines three types
of address spaces. The first, configuration address
space, is a physical address space that is intended as
a means for powerup software to identify agents and
allocate them address space. The second, I/O address
space, is intended for mapping I/O control functions.
The third, memory address spaces, is intended for bulk
data transfer. It has features to facilitate this, such as
special commands for cache implementation, large
page sizes, and mechanisms for prefetching. The PCI
bus core handles all three address space types as both
a Master and a Target.
Byte Alignment.
On all write operations (configuration,
I/O, and memory) for both the PCI bus core’s Master
and Target functions, byte enables are fully imple-
mented from/to the FPGA interface. Note, however,
that even though the PCI bus core implements the abil-
ity to control byte enables for the memory write and
invalidate instruction, the PCI Specification requires
that this instruction assert all byte enables, and this is
the FPGA application’s responsibility. On read opera-
tions, the utility of byte enables is more dubious since
the data must be enroute from the PCI bus Target to
Master, at the time that the corresponding byte enables
are enroute from the PCI bus Master to Target (unless
wait-states are inserted). The PCI bus core, therefore,
does not implement full-byte enable control for Target
reads, and limited for Master reads.
For the OR3TP12, byte enables on Master read burst
operations must always be asserted; nonburst Master
reads may manipulate the byte enables. Byte enables
on Target read operations are ignored, in accordance
with PCI Specification 2.1, Section 3.2.3. All Master
burst read and write addresses must be aligned on
64-bit boundaries. Single read and write addresses can
be aligned on 32-bit boundaries.
Device Selection (devseln)
The Target is responsible for decoding the address of a
M
aster’s request by asserting the PCI bus signal
devseln
.
devseln
may be asserted one, two, or three
clocks after the address phrase of a transaction, corre-
sponding to fast, medium, or slow decode, respectively.
The PCI bus core’s Target is capable of performing a
medium-speed decode response. The decode
response speed has a significant impact on the overall
latency and bandwidth of nonburst PCI transactions. Its
impact decreases greatly for burst transactions, partic-
ularly for burst lengths of the size of the PCI bus core’s
FIFOs.
Address/Data Stepping
Stepping is an optional feature added to the PCI Speci-
fication to accommodate agents whose bus drive capa-
bility is insufficient to handle large groups of signals
changing state in one clock cycle. Continuous stepping
allows weak drivers multiple cycles for signal transition.
Discrete stepping partitions the bus into two or more
groups of bits that transition on successive clock
cycles. However, stepping exacts a heavy toll on perfor-
mance, cutting maximum bandwidth by at least 50%
and increasing latency. The PCI core is designed for
maximum throughput with high-performance buffers, so
stepping is unnecessary and not implemented. The
wait cycle control, bit seven of the command register, is
therefore hardwired to a 0.
Interrupt Acknowledge
The interrupt acknowledge command is a read by the
system CPU implicitly addressed to the system inter-
rupt controller. Other agents, including the PCI bus
core, are not required to implement this instruction; the
PCI bus core’s Master does not generate it, and its Tar-
get ignores it.
Arbitration Parking
The PCI Specification requires that all Master agents
properly handle bus parking, which means that when
that agent receives an asserted
gntn
without the agent
having asserted its
reqn
, the agent still must drive sig-
nal
par
and buses
ad
and
c_ben
to a stable value. The
PCI bus core meets this requirement.
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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