參數(shù)資料
型號(hào)： MT9046
廠(chǎng)商： Zarlink Semiconductor Inc.
元件分類(lèi)： 基準(zhǔn)電壓源/電流源
英文描述： T1/E1 System Synchronizer with Holdover
中文描述： T1/E1的系統(tǒng)同步的緩繳暫繳稅
文件頁(yè)數(shù)： 8/34頁(yè)
文件大小： 508K
代理商： MT9046
MT9046
Data Sheet
8
Zarlink Semiconductor Inc.
The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384 MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
Figure 5 - Output Interface Circuit Block Diagram
The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs
are locked to one another for all operating states, and are also locked to the selected input reference in Normal
Mode. See Figures 14 & 16.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30 pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)
when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See AC Electrical
Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the
incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output
signal locked to the input signal. The holdover output signal in the MT9046 is based on the incoming signal 30 ms
minimum to 60 ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16 MHz
12 MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12 MHz
19 MHz
C6o
C19o
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