參數(shù)資料
型號: MT9046
廠商: Zarlink Semiconductor Inc.
元件分類: 基準電壓源/電流源
英文描述: T1/E1 System Synchronizer with Holdover
中文描述: T1/E1的系統(tǒng)同步的緩繳暫繳稅
文件頁數(shù): 17/34頁
文件大小: 508K
代理商: MT9046
MT9046
Data Sheet
17
Zarlink Semiconductor Inc.
Figure 7 - Control State Diagram
MT9046 and Network Specifications
The MT9046 fully meets all applicable PLL requirements (intrinsic jitter/wander, jitter/wander tolerance,
jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and
MTIE during reference rearrangement) for the following specifications.
1. Bellcore GR-1244-CORE June 1995 for Stratum 4 Enhanced and Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum 4 Enhanced and Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 4 Enhanced and Stratum 4
4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
Phase Re-Alignment
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
NOTES:
(XXX)
{A}
MS2 MS1 RSEL
Invalid Reference Signal
Movement to Normal State from any
state requires a valid input signal
{A}
{A}
S0
Freerun
(10X)
S2H
Holdover
Secondary
(011)
S1H
Holdover
Primary
(010)
S2
Normal
Secondary
(001)
S1
Normal
Primary
(000)
(PCCi=0)
(PCCi=1)
S1A
Auto-Holdover
Primary
(000)
S2A
Auto-Holdover
Secondary
(001)
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