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參數資料
| 型號： | MT9046 |
| 廠商： | Zarlink Semiconductor Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | T1/E1 System Synchronizer with Holdover |
| 中文描述： | T1/E1的系統(tǒng)同步的緩繳暫繳稅 |
| 文件頁數： | 3/34頁 |
| 文件大小： | 508K |
| 代理商： | MT9046 |
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MT9046
Data Sheet
3
Zarlink Semiconductor Inc.
Pin Description
Pin #
Name
Description
1,10,
23,31
V
SS
Ground.
0 Volts. (Vss pads).
2
RST
Reset (Input).
A logic low at this input resets the MT9046. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low for a minimum of 300 ns. While the RST pin is low, all frame pulses
except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high.
The RST, TSP, C6o and C16o are at logic low during reset. The C19o is free-running
during reset. Following a reset, the input reference source, output clocks and frame pulses
are phase aligned as shown in Figure 13.
3
TCLR
TIE Circuit Reset (Input).
A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase as shown in
Figure 13. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally
pulled down to VSS.
4
NC
No Connection.
Leave open Circuit
5
SEC
Secondary Reference (Input).
This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz,
2.048 MHz or 19.44 MHz) may be used. The selection of the input reference is based upon
the MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to V
DD
.
Primary Reference (Input).
See pin description for SEC. This pin is internally pulled up to
V
DD
.
Positive Supply Voltage.
+3.3 V
DC
nominal.
6
PRI
7,17
28,35
V
DD
8
OSCo
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20 MHz crystal is
connected from this pin to OSCi, see Figure 9. For clock oscillator operation, this pin is left
unconnected, see Figure 8.
9
OSCi
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20 MHz crystal is
connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is
connected to a clock source, see Figure 8.
11
F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8 kHz 61 ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 14.
12
F0o
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output).
This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 14.
13
RSP
Receive Sync Pulse (CMOS Output).
This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
14
TSP
Transmit Sync Pulse (CMOS Output).
This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
15
F8o
Frame Pulse (CMOS Output).
This is an 8 kHz 122 ns active high framing pulse, which
marks the beginning of a frame. See Figure 14.
16
C1.5o
Clock 1.544 MHz (CMOS Output).
This output is used in T1 applications.
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