參數(shù)資料
型號(hào)： MT9046
廠商： Zarlink Semiconductor Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： T1/E1 System Synchronizer with Holdover
中文描述： T1/E1的系統(tǒng)同步的緩繳暫繳稅
文件頁(yè)數(shù)： 4/34頁(yè)
文件大?。?/td> 508K
代理商： MT9046
MT9046
Data Sheet
4
Zarlink Semiconductor Inc.
18
LOCK
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked to
the input reference.
19
C2o
Clock 2.048 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s.
20
C4o
Clock 4.096 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
21
C19o
Clock 19.44 MHz (CMOS Output).
This output is used in OC3/STS3 applications.
22
FLOCK
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference
(less than 500 ms locking time).
24
IC
Internal Connection.
Tie low for normal operation.
25
C8o
Clock 8.192 MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192 Mb/s.
26
C16o
Clock 16.384 MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384 MHz clock.
27
C6o
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
29
HOLD
OVER
Holdover (CMOS Output).
This output goes to a logic high whenever the PLL goes into
holdover mode.
30
PCCi
Phase Continuity Control Input (Input).
The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and
Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.
See Table 4.
32
NC
No connection.
Leave open circuit
33,34
IC
Internal Connection.
Tie low for normal operation.
36
MS2
Mode/Control Select 2 (Input).
This input determines the state (Normal, Holdover or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
37
MS1
Mode/Control Select 1 (Input).
The logic level at this input is gated in by the rising edge of
F8o. See pin description for MS2. This pin is internally pulled down to VSS.
38
RSEL
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to VSS.
39
IC
Internal Connection.
Tie low for normal operation.
40
FS2
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. See Table 1.
41
FS1
Frequency Select 1 (Input).
See pin description for FS2.
42
IC
Internal Connection.
Tie low for normal operation.
43
NC
No Connection.
Leave open Circuit
44
TDO
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Pin Description (continued)
Pin #
Name
Description
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