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參數(shù)資料
| 型號(hào)： | ML53812-2 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 668K |
| 代理商： | ML53812-2 |
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Oki Semiconductor
5.13 CT Bus Streams
Connection to all 32 CT Bus streams is supported without restriction. The upper 16 streams run at 8Mb/s
while the lower 16 may be configured, in groups of four, to operate at 8Mb/s, 4Mb/s, or 2Mb/s.
5.14 CT_D disable
The user may disable all CT_D output streams in the event of a bus timing error. When enabled, an error
on the slave PLL reference source causes the CT_D streams to be tri-stated until an entire frame time
without errors has passed. The CT_D_DISABLE signal is provided to link multiple ML53812-2 devices.
5.15 Diagnostic Mode
Diagnostic mode tri-states all CT Bus signals while internally looping-back CT Bus outputs to inputs.
This mode allows a printed circuit board containing the ML53812-2 to be thoroughly tested without
causing CT Bus errors.
5.16 Interrupts
The ML53812-2 supports the following interrupt sources:
CT Bus A Error
CT Bus B Error
CT Bus A (CT Bus B) error is detected when CT_C8_A (CT_C8_B) rising edge does not occur within
35 ns of the expected time, relative to the previous period (see Figure 4) or when CT_FRAME_A_N
(CT_FRAME_B_N) low does not occur when expected. (See ECTF H.100/H.110 Specifications for
details on CT_C8_(A/B) and CT_FRAME_(A/B)_N signal timing.)
SCbus Error
SCbus error is detected when SCLK does not transition at close to the expected frequency (C_[25:24]
determines the expected frequency) or FR_COMP_N low does not occur when expected. (See ECTF
H.100/H.110 Specifications for details on SCLK, SCLKx2, and FR_COMP_N signal timing.)
MVIP Error
MVIP error is detected when C2 does not transition at close to 2 MHz, or FR_COMP_N low does not
occur when expected. (See ECTF H.100/H.110 Specifications for details on C2 and FR_COMP_N sig-
nal timing).
Master PLL Out of Lock Error
Master PLL error is detected when the master PLL is not locked to the selected Reference defined by
C_[43:40].
Frame Boundary
Frame Boundary interrupt is not an error condition, and occurs when the internal state machine
crosses a frame boundary.
GPIO
GPIO interrupt occurs when one or more of the GPIO inputs match the programmed latch polarity,
defined by C_[167:136].
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