參數(shù)資料
型號(hào)： ML53812-2
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176
封裝： LQFP-176
文件頁(yè)數(shù)： 57/64頁(yè)
文件大?。?/td> 668K
代理商： ML53812-2
s ML53812-2 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
56
Oki Semiconductor
7.6 Clock Skew Requirements
(Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
(H.100) Max Skew between CT_C8 "A" and "B"
Tskc8
±10 ±
Φ
ns
[1] [2] [3] [4]
1.
Test Load – 200 pF.
2.
Assumes "A" and "B" masters in adjacent slots.
3.
When static skew is 10nS and, in the same clock cycle, each clock performs a 10nS phase correction in opposite directions, a maximum skew of
30nS will occur during that clock cycle.
4.
Meeting the skew requirements in Table 2 and the requirements of Section 2.3 (in the H.100/H.110 Specifications, Rev. 1.0) could require the
PLL’s generating CT_C8 to have different time constants when acting as primary and secondary clock masters.
(H.110) Max Skew between CT_C8 "A" and "B"
Tskc8
±10 ±
Φ
ns
5.
Test Load - "A" load = "B" load.
(H.100) Max Skew between CT_C8_A and any
compatibility clock
Tskcomp
±5
ns
(H.110) Max Skew between CT_C8_A and any
compatibility clock
Tskcomp
±5
ns
Figure 15. Clock Skew Requirements
CT_C8_A
CT_C8_B
Vt+
Tskc8
CT_C8_A
Inter-operability Clocks
Vt+
Tskcomp
Vt-
Tskcomp
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