DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號(hào)： MCZ33905BD3EK
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 78/106頁(yè)
文件大?。?/td> 0K
描述： IC SBC CAN HS 3.3V 54SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 28 V
封裝/外殼： 54-SSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 54-SOICW-EP
包裝： 管件
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
73
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
SPECIFIC MODE REGISTER
The SPE MODE Register is used for the Following
Operation
- Set the device in RESET mode, to exercise or test the
RESET functions.
- Go to INIT mode, using the Secure SPi command.
- Go to FLASH mode (in this mode the watchdog timer can
be extended up to 32 s).
- Activate the SAFE pin by S/W.
This mode (called Special mode) is accessible from the
secured SPI command, which consist of 2 commands:
1) reading a random code and
2) then write the inverted random code plus mode
selection or SAFE pin activation:
Return to INIT mode is done as follow (this is done from
Normal mode only):
1) Read random code:
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits
random code)
2) Write INIT mode + random code inverted
MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52
HH] (RIX = random code inverted)
MISO : xxxx xxxx xxxx xxxx (don’t care)
SAFE pin activation: SAFE pin can be set low, only in INIT
mode, with following commands:
1) Read random code:
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits
random code)
2) Write INIT mode + random code bits 5:4 not inverted
and random code bits 3:0 inverted
MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52
HH] (RIX = random code inverted)
MISO : xxxx xxxx xxxx xxxx (don’t care)
Return to Reset or Flash mode is done similarly to the go
to INIT mode, except that the b7 and b6 are set according to
the table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to
Flash).
Table 21. Specific Mode Register, SPE_MODE
MOSI First Byte [15-8]
[b_15 b_14] 01_001 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 001 P
Sel_Mod[1]
Sel_Mod[0]
Rnd_C5b
Rnd_C4b
Rnd_C3b
Rnd_C2b
Rnd_C1b
Rnd_C0b
Default state
0
Condition for default
POR
Bit
Description
b7, b6
Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command.
00
RESET mode
01
INIT mode
10
FLASH mode
11
N/A
b5....b0
[Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE MODE Register read command.
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