Analog Integrated Circuit Device Data
Freescale Semiconductor
27
33903/4/5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V
VSUP 28 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI TIMING
SPI Operation Frequency (MISO cap = 50 pF)
FREQ
0.25
-
4.0
MHz
SCLK Clock Period
tPCLK
250
-
N/A
ns
SCLK Clock High Time
tWSCLKH
125
-
N/A
ns
SCLK Clock Low Time
tWSCLKL
125
-
N/A
ns
Falling Edge of CS to Rising Edge of SCLK
“C” version
All others
tLEAD
30
550
-
N/A
ns
Falling Edge of SCLK to Rising Edge of CS
tLAG
30
-
N/A
ns
MOSI to Falling Edge of SCLK
tSISU
30
-
N/A
ns
Falling Edge of SCLK to MOSI
tSIH
30
-
N/A
ns
MISO Rise Time (CL = 50 pF)
tRSO
-
30
ns
MISO Fall Time (CL = 50 pF)
tFSO
-
30
ns
Time from Falling to MISO Low-impedance
Time from Rising to MISO High-impedance
tSOEN
tSODIS
-
30
ns
Time from Rising Edge of SCLK to MISO Data Valid
tVALID
-
30
ns
Delay between falling and rising edge on CS
“C” version
All others
tCSLOW
1.0
5.5
-
N/A
s
CS Chip Select Low Timeout Detection
tCS-TO
2.5
-
ms
SUPPLY, VOLTAGE REGULATOR, RESET
VSUP undervoltage detector threshold deglitcher
tVS_LOW1/
2_DGLT
30
50
100
s
Rise time at turn ON. VDD from 1.0 to 4.5V. 2.2 F at the VDD pin.
tRISE-ON
50
250
800
s
Deglitcher time to set RST pin low
tRST-DGLT
20
30
40
s
RESET PULSE DURATION
VDD undervoltage (SPI selectable)
short, default at power on when BATFAIL bit set
medium
medium long
long
tRST-PULSE
0.9
4.0
8.5
17
1.0
5.0
10
20
1.4
6.0
12
24
ms
Watchdog reset
tRST-WD
0.9
1.0
1.4
ms
I/O INPUT
Deglitcher time (Guaranteed by design)
tIODT
19
30
41
s
VSENSE INPUT
Undervoltage deglitcher time
tBFT
30
-
100
s