BEHAVIOR AT POWER UP AND POWER DOWN SAFE Mode B" />
參數(shù)資料
型號(hào)： MCZ33905BD3EK
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 57/106頁(yè)
文件大小： 0K
描述： IC SBC CAN HS 3.3V 54SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 28 V
封裝/外殼： 54-SSOP（0.295"，7.50mm 寬）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 54-SOICW-EP
包裝： 管件
安裝類(lèi)型： 表面貼裝
Analog Integrated Circuit Device Data
54
Freescale Semiconductor
33903/4/5
FAIL-SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
SAFE Mode B1, B2 and B3 Illustration
Figure 32 illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug
resistor or SPI configuration.
Figure 32. SAFE Modes B1, B2, or B3 Behavior Illustration
DBG resistor => safe state B1
VDD
RST
SAFE
CAN bus
CAN bus idle time
I/O-1
I/O-1 high to low transition
DBG resistor => safe state B2
DBG resistor => safe state B3
CAN bus
CAN bus idle time
I/O-1
I/O-1 high to low transition
step 2:
RST
VDD
failure event, i.e. watchdog
SAFE
OFF state ON state
8 x 256 ms delay time to enter in SAFE mode
to evaluate resistor at the DBG pin
and monitor ECU external events
1st
8th
2nd
step 1: Failure illustration
RST
VDD
failure event, VDD low
SAFE
OFF state ON state
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
VDD_UV TH
100 ms
GND
RST
VDD
failure event, Reset s/c GND
SAFE
OFF state
ON state
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at DBG pin
and monitor ECU external events
2.5 V
100 ms
VDD
RST
SAFE
VDD OFF
RST
SAFE
VDD
If VDD failure recovered
VDD < VDD_UV TH
VDD OFF
GND
step 3: Consequences for VDD
If Reset s/c GND recovered
Behavior illustration for the safe state B (RDG > 10 kohm)
Wa
ke
-up
ECU
e
xternal
con
diti
on
me
t =>
V DD
dis
able
ECU external event to
RDBG resistor or
disable VDD based on
SPI configuration
Exclusive detection of
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