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參數(shù)資料
| 型號： | MCZ33905BD3EK |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 59/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SBC CAN HS 3.3V 54SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 應(yīng)用： | 系統(tǒng)基礎(chǔ)芯片 |
| 接口： | CAN，LIN |
| 電源電壓： | 5.5 V ~ 28 V |
| 封裝/外殼： | 54-SSOP（0.295"，7.50mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 54-SOICW-EP |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
56
Freescale Semiconductor
33903/4/5
CAN INTERFACE
CAN INTERFACE DESCRIPTION
When the CAN interface is in Normal mode, the driver has
two states: recessive or dominant. The driver state is
controlled by the TXD pin. The bus state is reported through
the RXD pin.
When TXD is high, the driver is set in the recessive state,
and CANH and CANL lines are biased to the voltage set with
5 V-CAN divided by 2, or approx. 2.5 V.
When TXD is low, the bus is set into the dominant state,
and CANL and CANH drivers are active. CANL is pulled low
and CANH is pulled high.
The RXD pin reports the bus state: CANH minus the CANL
voltage is compared versus an internal threshold (a few
hundred mV).
If “CANH minus CANL” is below the threshold, the bus is
recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is
dominant and RXD is set low.
The SPLIT pin is active and provides a 2.5 V biasing to the
SPLIT output.
TXD/RXD Mode and Slew Rate Selection
The CAN signal slew rate selection is done via the SPI. By
default and if no SPI is used, the device is in the fastest slew
rate. Three slew rates are available. The slew rate controls
the recessive to dominant, and dominant to recessive
transitions. This also affects the delay time from the TXD pin
to the bus and from the bus to the RXD. The loop time is thus
affected by the slew rate selection.
Minimum Baud Rate
The minimum baud rate is determined by the shortest TXD
permanent dominant timing detection. The maximum number
of consecutive dominant bits in a frame is 12 (6 bits of active
error flag and its echo error flag).
The shortest TXD dominant detection time of 300
s lead
to a single bit time of: 300
s / 12 = 25 s.
So the minimum Baud rate is 1 / 25
s = 40 kBaud.
Sleep Mode
Sleep mode is a reduced current consumption mode.
CANH and CANL drivers are disabled and CANH and CANL
lines are terminated to GND via the RIN resistor, the SPLIT
pin is high-impedance. In order to monitor bus activities, the
CAN Wake-up receiver can be enabled. It is supplied
internally from VSUP/2.
Wake-up events occurring on the CAN bus pin are
reporting by dedicated flags in SPI and by INT pulse, and
results in a device Wake-up if the device was in LP mode.
When the device is set back into Normal mode, CANH and
CANL are set back into the recessive level. This is illustrated
in Figure 34.
.
Figure 34. Bus Signal in TXD/RXD and LP Mode
Wake-up
When the CAN interface is in Sleep mode with Wake-up
enabled, the CAN bus traffic is detected. The CAN bus Wake-
up is a pattern Wake-up. The Wake-up by the CAN is enabled
or disabled via the SPI.
CANL
CANH
TXD
RXD
2.5 V
CANL-DOM
CANH-DOM
CANL/CANH-REC
2.5 V
High ohmic termination (50 kohm) to GND
SPLIT
Dominant state
Recessive state
Bus Driver
Receiver
(bus dominant set by other IC)
High-impedance
Normal or Listen Only mode
Go to sleep,
CANH-CANL
Sleep or Stand-by mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33905BD3EKR2 | 功能描述:CAN 接口集成電路 3.3V SBC HSCAN DUAL LIN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33905BD3R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
| MCZ33905BD5EK | 功能描述:CAN 接口集成電路 5.0V SBC HSCAN DUAL LIN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33905BD5EKR2 | 功能描述:CAN 接口集成電路 5.0V SBC HSCAN DUAL LIN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33905BD5R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
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