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參數(shù)資料
| 型號： | MCZ33905BD3EK |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 62/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SBC CAN HS 3.3V 54SOIC |
| 標準包裝： | 26 |
| 應用： | 系統(tǒng)基礎(chǔ)芯片 |
| 接口： | CAN，LIN |
| 電源電壓： | 5.5 V ~ 28 V |
| 封裝/外殼： | 54-SSOP（0.295"，7.50mm 寬）裸露焊盤 |
| 供應商設(shè)備封裝： | 54-SOICW-EP |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
59
33903/4/5
CAN INTERFACE
CAN BUS FAULT DIAGNOSTIC
DETECTION PRINCIPLE
In the recessive state, if one of the two bus lines are
shorted to GND, VDD (5.0 V), or VBAT, the voltage at the
other line follows the shorted line, due to the bus termination
resistance. For example: if CANL is shorted to GND, the
CANL voltage is zero, the CANH voltage measured by the Hg
comparator is also close to zero.
In the recessive state, the failure detection to GND or
VBAT is possible. However, it is not possible with the above
implementation to distinguish which of the CANL or CANH
lines are shorted to GND or VBAT. A complete diagnostic is
possible once the driver is turned on, and in the dominant
state.
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of the
recessive and dominant states to properly recognize the bus
failure. The error will be fully detected after five cycles of the
recessive-dominant states. As long as the failure detection
circuitry has not detected the same error for five recessive-
dominant cycles, the error is not reported.
BUS CLAMPING DETECTION
If the bus is detected to be in dominant for a time longer
than (TDOM), the bus failure flag is set and the error is
reported in the SPI.
This condition could occur when the CANH line is shorted
to a high-voltage. In this case, current will flow from the high-
voltage short-circuit, through the bus termination resistors
(60
), into the SPLIT pin (if used), and into the device CANH
and CANL input resistors, which are terminated to internal
2.5 V biasing or to GND (Sleep mode).
Depending upon the high-voltage short-circuit, the number
of nodes, usage of the SPLIT pin, RIN actual resistor and
mode state (Sleep or Active) the voltage across the bus
termination can be sufficient to create a positive dominant
voltage between CANH and CANL, and the RXD pin will be
low. This would prevent start of any CAN communication and
thus, proper failure identification requires five pulses on TXD.
The bus dominant clamp circuit will help to determine such
failure situation.
RXD Permanent Recessive Failure (does not apply
to “C version”)
The aim of this detection is to diagnose an external
hardware failure at the RXD output pin and ensure that a
permanent failure at RXD does not disturb the network
communication. If RXD is shorted to a logic high signal, the
CAN protocol module within the MCU will not recognize any
incoming message. In addition, it will not be able to easily
distinguish the bus idle state and can start communication at
any time. In order to prevent this, RXD failure detection is
necessary. When a failure is detected, the RXD high flag is
set and CAN switches to receive only mode.
Figure 39. RXD Path Simplified Schematic, RXD Short to VDD Detection
Implementation for Detection
The implementation senses the RXD output voltage at
each low to high transition of the differential receiver.
Excluding the internal propagation delay, the RXD output
should be low when the differential receiver is low. When an
external short to VDD at the RXD output, RXD will be tied to
a high level and can be detected at the next low to high
transition of the differential receiver.
As soon as the RXD permanent recessive is detected, the
RXD driver is deactivated.
L5 (threshold VDD -0.43 V)
H5 (threshold VDD -0.43 V)
L5 (threshold VDD -0.43 V)
H5 (threshold VDD -0.43 V)
No failure
0
CANL to 5.0 V
1
CANH to 5.0 V
1
0
1
Table 10. Failure Detection Truth Table
Failure Description
Driver Recessive State
Driver Dominant State
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
CANH
CANL
Diff
VDD
Rxsense
RXD driver
RXD
TXD
TXD driver
60
VDD
Logic
Diag
CANL&H
Diff output
RXD output
RXD short to VDD
Prop delay
RXD flag
RXD flag latched
VDD/2
Sampling
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33905BD3EKR2 | 功能描述:CAN 接口集成電路 3.3V SBC HSCAN DUAL LIN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33905BD3R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
| MCZ33905BD5EK | 功能描述:CAN 接口集成電路 5.0V SBC HSCAN DUAL LIN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33905BD5EKR2 | 功能描述:CAN 接口集成電路 5.0V SBC HSCAN DUAL LIN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33905BD5R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
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