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參數(shù)資料
| 型號(hào)： | MCHC908RK2CSDR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SSOP-20 |
| 文件頁(yè)數(shù)： | 163/181頁(yè) |
| 文件大小： | 2384K |
| 代理商： | MCHC908RK2CSDR2 |
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Internal Clock Generator Module (ICG)
Data Sheet
MC68HC908RK2 — Rev. 5.0
82
Internal Clock Generator Module (ICG)
MOTOROLA
Settling time depends primarily on how many corrections it takes to change the
clock period, and the period of each correction. Since the corrections require four
periods of the low-frequency base clock (4*
τ
IBASE), and since ICLK is N (the ICG
multiply factor for the desired frequency) times faster than IBASE, each correction
takes 4*N*
τ
ICLK. The period of ICLK, however, will vary as the corrections occur.
6.4.6.1 Settling to Within 15%
When the error is greater than 15%, the filter takes eight corrections to double or
halve the clock period. Due to how the DCO increases or decreases the clock
period, the total period of these eight corrections is approximately 11 times the
period of the fastest correction. (If the corrections were perfectly linear, the total
period would be 11.5 times the minimum period; however, the ring must be slightly
non-linear.) Therefore, the total time it takes to double or halve the clock period is
44*N*tICLKFAST.
If the clock period needs more than doubled or halved, the same relationship
applies, only for each time the clock period needs doubled, the total number of
cycles doubles.
That is, when transitioning from fast to slow:
Going from the initial speed to half speed takes 44*N*tICLKFAST
From half speed to quarter speed takes 88*N*tICLKFAST
Going from quarter speed to eighth speed takes 176*N*tICLKFAST, and so
on.
This series can be expressed as (2x–1)*44*N*tICLKFAST, where x is the number of
times the speed needs doubled or halved. Since 2x happens to be equal to
τ
ICLKSLOW/τICLKFAST, the equation reduces to 44*N*(τICLKSLOW-τICLKFAST). Note
that increasing speed takes much longer than decreasing speed since N is higher.
This can be expressed in terms of the initial clock period (
τ
1) minus the final clock
period (
τ
2) as such:
6.4.6.2 Settling to Within 5%
Once the clock period is within 15% of the desired clock period, the filter starts
making smaller adjustments. When between 15% and 5% error, each correction
will adjust the clock period between 1.61% and 2.94%. In this mode, a maximum
of eight corrections will be required to get to less than 5% error. Since the clock
period is relatively close to desired, each correction takes approximately the same
period of time, or 4*
τ
IBASE. At this point, the internal clock stable bit (ICGS) will be
set and the clock frequency is usable, although the error will be as high as 5%. The
total time to this point is:
τ
15
abs 44N
τ
1
τ
2
–
()
[]
=
τ
5
abs 44N
τ
1
τ
2
–
()
[] 32τ
IBASE
+
=
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