MOTOROLA
2-8
PINS AND CONNECTIONS
M68HC11
REFERENCE MANUAL
Although the MC68HC11A8 is a CMOS device, very fast signal transitions are present
on many of the pins. Even when the MCU is operating at slow clock rates, short rise
and fall times are present. Depending upon the loading on these fast signals, signifi-
cant short-duration current demands can be placed on the MCU power supply. Special
care must be taken to provide good power-supply bypassing at the MCU.
The faster edge times in the MC68HC11A8 generally place greater demands on by-
passing than earlier NMOS MCU designs. A typical expanded-mode system should in-
clude a 1-
μ
F capacitor and a separate 0.01-
μ
F capacitor. Both these capacitors
should be as close (physically and electrically) as possible to the MC68HC11A8 and
should have good high-frequency characteristics (i.e., not old-technology dipped ce-
ramic disc). The 1-
μ
F capacitor primarily supplies charge for bus switching through a
very low-impedance path (minimum-length runners). Without this bypass, there could
be very large voltage drops in the circuit board runners to the MCU due to the very high
(although very short duration) current spike caused by several MCU pins simulta-
neously switching from one level to the other. The separate 0.01-
μ
F capacitor is in-
cluded because the larger 1-
μ
F capacitor is typically not as good at snubbing very
high-frequency (low energy) noise. These are only general recommendations. Some
lightly loaded single-chip systems may work quite well with a single 0.1-
μ
F bypass ca-
pacitor; whereas, more heavily loaded expanded-mode systems may require more
elaborate bypassing measures.
It is easier and less expensive to approach power-supply layout and bypassing as a
preventive measure from the beginning of a design than to locate and correct a noise
problem in a marginal design. Problems related to inadequate power-supply layout
and bypassing are very difficult to locate and correct, but, if reasonable care is taken
from the start of a design, noise should not arise as a problem.
2.2.2 Mode Select Pins (MODB/V
STBY
and MODA/LIR
)
The mode B/standby RAM supply (MODB/V
STBY
) pin functions as both a mode select
input pin and a standby power-supply pin. The mode A/load instruction register (MO-
DA/LIR) pin is used to select the MCU operating mode while the MCU is in reset, and
it operates as a diagnostic output signal while the MCU is executing instructions.
The hardware mode select mechanism starts with the logic levels on the MODA and
MODB pins while the MCU is in the reset state. The logic levels on the MODA and
MODB pins are fed into the MCU via a clocked pipeline path. The levels captured are
those that were present part of a clock cycle before the RESET pin rose, which as-
sures there will be a zero hold-time requirement on the mode select pins relative to the
rising edge at the RESET pin. The captured levels determine the logic state of the spe-
cial mode (SMOD) and mode A select (MDA) control bits in the highest priority inter-
rupt (HPRIO) register. These two control bits actually control the logic circuits involved
in hardware mode selection. Mode A selects between single-chip modes and expand-
ed modes; mode B selects between the normal variation and the special variation of
the chosen operating mode. Bootstrap mode is the special variation of single-chip
mode, and special test is the special variation of expanded mode.
Table 2-1
summa-
rizes the operation of the mode pins and mode control bits.