參數(shù)資料
型號： MC68EC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 123/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標準包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Memory Management Unit
MOTOROLA
M68060 USER’S MANUAL
4-25
CM—Cache Mode
This field selects the cache mode and accesses serialization as follows:
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Noncachable, Precise
11 = Noncachable, Imprecise
Section 5 Caches provides detailed information on caching modes.
FC2—Function Code Bit 2 (Supervisor/User)
This bit contains the function code corresponding to the logical address in this entry. FC2
is set for supervisor mode accesses and cleared for user mode accesses.
G—Global
When set, this bit indicates the entry is global. Global entries are not invalidated by the
PFLUSH instruction variants that specify nonglobal entries, even when all other selection
criteria are satisfied.
Logical Address
This 16-bit field contains the most significant logical address bits for this entry. All 16 bits
of this field are used in the comparison of this entry to an incoming logical address when
the page size is 4 Kbytes. For 8-Kbytes pages, the least significant bit of this field is
ignored.
M—Modified
The modified bit is set when a valid write access to the logical address corresponding to
the entry occurs. If the M-bit is clear and a write access to this logical address is
attempted, the MC68060 suspends the access, initiates a table search to set the M-bit in
the page descriptor, and writes over the old ATC entry with the current page descriptor
information. The MMU then allows the original write access to be performed. This proce-
dure ensures that the first write operation to a page sets the M-bit in both the ATC and the
page descriptor in the translation tables, even when a previous read operation to the page
had created an entry for that page in the ATC with the M-bit clear.
Physical Address
The upper bits of the translated physical address are contained in this field.
U1
U0
CM
M
W
PHYSICAL ADDRESS*
ENTRY
V
G
FC2
LOGICAL ADDRESS*
TAG
*FOR 4-KBYTE PAGE SIZES, THIS FIELD USES ADDRESS BITS 31–12; FOR 8-KBYTE PAGE SIZES, BITS 31–13.
Figure 4-20. ATC Entry and Tag Fields
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