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| 型號(hào)： | MC68EC060RC66 |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 12/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 66MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類(lèi)型： | M680x0 32-位 |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤(pán) |
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Caches
5-10
M68060 USER’S MANUAL
MOTOROLA
5.5.3 Read Hit
On a read hit, the appropriate cache provides the data to the requesting pipe unit. In most
cases no bus transaction is performed, and the state of the cache line does not change.
However, when a writethrough read hit to a line containing dirty data occurs, the dirty line is
pushed and the cache line state changes to valid before the data is provided to the request-
ing pipe unit.
A snooped external read hit invaildates the cache line that is hit.
5.5.4 Write Hit
The cache controller handles processor writes that hit in the cache differently for
writethrough and copyback pages. For write hits to a writethrough page, the portions of the
cache line(s) corresponding to the size of the access are updated with the data, and the data
is also written to external memory. The cache line state does not change. A writethrough
access to a line containing dirty data results in the dirty line being pushed and then witten to
memory. If the access is copyback, the cache controller updates the cache line and sets the
D-bit for the line. An external write is not performed, and the cache line state changes to, or
remains in, the dirty state.
An alternate bus master can assert the SNOOP signal for a write that it initiates, which will
invalidate any corresponding entry in the internal cache.
5.6 CACHE COHERENCY
The MC68060 provides several different mechanisms to assist in maintaining cache coher-
ency in multimaster systems. Both writethrough and copyback memory update techniques
are supported to maintain coherency between the data cache and memory.
Alternate bus master accesses can reference data that the MC68060 may have cached,
causing coherency problems if the accesses are not handled properly. The MC68060
snoops the bus during alternate bus master transfers if SNOOP is asserted. Snoop hits
invalidate the cache line in all cases (read, write, long word, word, byte) for MOVE16 and
normal accesses. Since the processor may be accessing data in its caches even when it
does not have the bus, a snoop has priority over the processor, to maintain cache coher-
ency.
The snooping protocol and caching mechanism supported by the MC68060 requires that
pages shared with any other bus master be marked cachable writethrough or cache inhib-
ited (either precise or imprecise). This procedure allows each processor to cache shared
data for read access while forcing a processor write to shared data to appear as an external
write to memory, which the other processors can snoop. If shared data is stored in copyback
pages, cache coherency is not guaranteed.
Coherency between the instruction cache and the data cache must be maintained in soft-
ware since the instruction cache does not monitor data accesses. Processor writes that
modify code segments (i.e., resulting from self-modifying code or from code executed to
load a new page from disk) access memory through the data memory unit. Because the
instruction cache does not monitor these data accesses, stale data occurs in the instruction
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