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List of Illustrations
xvi
MC68307 USER’S MANUAL
MOTOROLA
4-3
General Form of Exception Stack Frame......................................................... 4-10
4-4
General Exception Processing Flowchart ........................................................ 4-11
4-5
Exception Vector Format.................................................................................. 4-12
4-6
Address Translated from 8-Bit Vector Number ................................................ 4-12
4-7
Supervisor Stack Order for Bus or Address Error Exception ........................... 4-19
5-1
Module Base Address, Decode Logic ................................................................ 5-3
5-2
Chip-Select Block Diagram ................................................................................ 5-6
5-3
External Bus Interface Logic .............................................................................. 5-9
5-4
Interrupt Controller Logic Block Diagram ......................................................... 5-15
6-1
Timer Block Diagram.......................................................................................... 6-2
7-1
M-Bus Interface Block Diagram ......................................................................... 7-2
7-2
M-Bus Transmission Signals.............................................................................. 7-3
7-3
M-Bus Clock Synchronization ............................................................................ 7-5
7-4
Flow-Chart of Typical M-Bus Interrupt Routine ................................................ 7-14
8-1
Simplified Block Diagram ................................................................................... 8-1
8-2
External and Internal Interface Signals .............................................................. 8-4
8-3
Baud Rate Generator Block Diagram................................................................. 8-5
8-4
Transmitter and Receiver Functional Diagram................................................... 8-6
8-5
Transmitter Timing Diagram............................................................................... 8-7
8-6
Receiver Timing Diagram................................................................................... 8-9
8-7
Looping Modes Functional Diagram ................................................................ 8-11
8-8
Multidrop Mode Timing Diagram ...................................................................... 8-13
8-9
Serial Mode Programming Flowchart............................................................... 8-32
9-1
Test Access Port Block Diagram........................................................................ 9-2
9-2
TAP Controller State Machine............................................................................ 9-3
9-3
Output Cell (O.Cell)............................................................................................ 9-6
9-4
Input Cell (I.Cell) ................................................................................................ 9-7
9-5
Output Control Cell (En.Cell).............................................................................. 9-7
9-6
Bidirectional Cell (IO.Cell) .................................................................................. 9-8
9-7
Bidirectional Cell (IOx0.Cell) .............................................................................. 9-8
9-8
General Arrangement for Bidirectional Pins....................................................... 9-9
9-9
Bypass Register ............................................................................................... 9-10
10-1
MC68307 Minimum System Configuration....................................................... 10-3
10-2
Hardware Setup ............................................................................................. 10-13
10-3
Master/Slave Responsibilities for the Master Transmit Block ........................ 10-15
10-4
Summary of M-Bus Activity for the Master Transmit Block ............................ 10-15
10-5
Master/Slave Responsibilities for the Master Receive Block ......................... 10-16
10-6
Summary of M-Bus Activity for the Master Receive Block ............................. 10-16
10-7
Memory Map after Swap Complete................................................................ 10-28
11-1
Drive Levels and Test Points for AC Specifications ......................................... 11-3
11-2
Clock Timing .................................................................................................... 11-5
11-3
Read Cycle Timing Diagram ............................................................................ 11-7
11-4
Write Cycle Timing Diagram ............................................................................ 11-8
11-5
Three-Wire Bus Arbitration Diagram ................................................................ 11-9
11-6
Two-Wire Bus Arbitration Timing Diagram..................................................... 11-10