![](http://datasheet.mmic.net.cn/30000/MC68307CFG16_datasheet_2368698/MC68307CFG16_13.png)
MOTOROLA
MC68307 USER’S MANUAL
xv
LIST OF ILLUSTRATIONS
1-1
MC68307 Block Diagram ................................................................................... 1-1
2-1
MC68307 Detailed Block Diagram ..................................................................... 2-2
3-1
Word Read Cycle Flowchart (16-Bit Bus)........................................................... 3-2
3-2
Byte Read Cycle Flowchart (16-Bit Bus) ............................................................ 3-3
3-3
Read and Write Cycle Timing Diagram (16-Bit Bus) .......................................... 3-3
3-4
Word and Byte Read Cycle Timing Diagram (16-Bit Bus).................................. 3-4
3-5
Word Write Cycle Flowchart (16-Bit Bus)........................................................... 3-5
3-6
Byte Write Cycle Flowchart (16-Bit Bus) ............................................................ 3-6
3-7
Word and Byte Write Cycle Timing Diagram...................................................... 3-6
3-8
Read-Modify-Write Cycle Flowchart................................................................... 3-8
3-9
Read-Modify-Write Cycle Timing Diagram ......................................................... 3-9
3-10
Interrupt Acknowledge Cycle – Address Bus ................................................... 3-11
3-11
Interrupt Acknowledge Cycle Timing Diagram ................................................. 3-12
3-12
8051-Compatible Read Cycle Signals.............................................................. 3-14
3-13
8051-Compatible Write Cycle Signals.............................................................. 3-14
3-14
Three-Wire Bus Arbitration Cycle Flowchart .................................................... 3-15
3-15
Two-Wire Bus Arbitration Cycle Flowchart....................................................... 3-16
3-16
Three-Wire Bus Arbitration Timing Diagram .................................................... 3-17
3-17
Two-Wire Bus Arbitration Timing Diagram ....................................................... 3-17
3-18
External Asynchronous Signal Synchronization............................................... 3-19
3-19
Bus Arbitration Unit State Diagrams................................................................. 3-20
3-20
Three-Wire Bus Arbitration Timing Diagram—Processor Active...................... 3-21
3-21
Three-Wire Bus Arbitration Timing Diagram—Bus Inactive ............................. 3-22
3-22
Three-Wire Bus Arbitration Timing Diagram—Special Case............................ 3-23
3-23
Two-Wire Bus Arbitration Timing Diagram—Processor Active ........................ 3-24
3-24
Two-Wire Bus Arbitration Timing Diagram—Bus Inactive................................ 3-25
3-25
Two-Wire Bus Arbitration Timing Diagram—Special Case .............................. 3-26
3-26
Bus Error Timing Diagram................................................................................ 3-28
3-27
Retry Bus Cycle Timing Diagram ..................................................................... 3-29
3-28
Halt Operation Timing Diagram........................................................................ 3-30
3-29
Reset Operation Timing Diagram..................................................................... 3-32
3-30
Fully Asynchronous Read Cycle ...................................................................... 3-33
3-31
Fully Asynchronous Write Cycle....................................................................... 3-33
3-32
Pseudo-Asynchronous Write Cycle.................................................................. 3-34
3-33
Pseudo-Asynchronous Read Cycle.................................................................. 3-34
3-34
Synchronous Read Cycle................................................................................. 3-37
3-35
Synchronous Write Cycle ................................................................................. 3-37
4-1
Programming Model ........................................................................................... 4-2
4-2
Status Register................................................................................................... 4-3
Thi d
t
t d
ith F
M k
4 0 4