![](http://datasheet.mmic.net.cn/30000/MC68307CFG16_datasheet_2368698/MC68307CFG16_113.png)
System Integration Module
5-18
MC68307 USER’S MANUAL
MOTOROLA
pointed to by the respective vector location should respond to the interrupt as appropriate,
including setting the PIR bit for that general-purpose interrupt input in the relevant LICRx
register, to indicate end-of-service.
reference to the external interrupt inputs.
NOTE
The latched interrupts need to be asserted for 2 clock falling
edges before they are considered valid, and are latched.
5.1.4.5 PERIPHERAL INTERRUPT HANDLING. The MC68307 on-chip I/O peripherals,
consisting of the two timer channels, the UART and the M-bus modules, are all capable of
being a source of interrupts. The interrupt controller logic coordinates the reception of
Interrupt Request signals from these three peripherals, the return of acknowledge
and the ultimate providing of vector information to the EC000 core processor.
The peripheral interrupt control register (PICR) allows the user to define which IPL each of
these four peripheral sources will use. The PIVR and UIVR allow the user to define a
particular vector number to be presented when the respective module receives an interrupt
acknowledge from the processor via the interrupt controller logic. These interrupt vector
registers are initialized upon cold reset with the uninitialized interrupt vector (hex $0F), and
must be programmed with the required vector number for normal operation. It is important
not to use reserved interrupt vector locations for this purpose, especially the ones used by
the MBAR and SCR register group.
In the case of the UART, there are multiple sources within the UART module which can
cause an interrupt, e.g., transmit ready, received character/buffer, break change of state. In
order to determine which of these should be serviced, the software interrupt handler must
read the relevant status register within the UART module. Note that the UART module has
its own vector register, allowing it to issue any programmed vector in response to an
interrupt acknowledge cycle.
In the case of the M-bus interface, there are multiple sources within the M-bus module which
can cause an interrupt, e.g., byte transferred, slave Rx address match, arbitration lost.
Again, the relevant status register within the M-bus interface module must be read to
elaborate on the condition being reported.
Finally, in the case of the timer module, there are multiple sources which can cause an
interrupt, e.g., compare or capture for each of the two functional timer channels. The timer
event registers can be read to determine the cause of the condition.